ADN2850(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADN2850 Datasheet PDF : 20 Pages
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ADN2850
SDO 1
16 15 14 13
12 PR
GND 2 ADN2850BCP 11 WP
VSS 3
V1 4
CHIP SCALE
PACKAGE
10 VDD
9 V2
5 67 8
PIN CONFIGURATIONS
CLK 1
SDI 2
16 RDY
15 CS
SDO 3
14 PR
GND 4 ADN2850BRU 13 WP
VSS 5
TOP VIEW
(Not To Scale) 12 VDD
V1 6
11 V2
W1 7
10 W2
B1 8
9 B2
ADN2850BCP PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 SDO
2 GND
3 VSS
4 V1
5 W1
6 B1
7 B2
8 W2
9 V2
10 VDD
11 WP
12 PR
13 CS
14 RDY
15 CLK
16 SDI
Serial Data Output Pin. Open-Drain output
requires external pull-up resistor. CMD_9 and
CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of
multiple packages.
Ground Pin, logic ground reference
Negative Supply. Connect to zero volts for
single-supply applications.
Log Output Voltage 1 generated from internal
diode configured transistor
Wiper terminal of RDAC1 ADDR
(RDAC1) = 0H.
B terminal of RDAC1
B terminal of RDAC2
Wiper terminal of RDAC2. ADDR
(RDAC2) = 1H.
Log Output Voltage 2 generated from internal
diode configured transistor
Positive Power Supply Pin
Write Protect Pin. When active low, WP
prevents any changes to the present register
contents, except PR and CMD_1 and CMD_8
will refresh the RDAC register from EEMEM.
Execute a NOP instruction before returning
to WP high.
Hardware Override Preset Pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 51210 until EEMEM loaded with
a new value by the user (PR is activated at
the logic high transition).
Serial Register chip select active low.
Serial register operation takes place when
CS returns to logic high.
Ready. Active high open-drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
Serial Input Register Clock Pin. Shifts in
one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time
on positive clock CLK edges. MSB loaded first.
ADN2850BRU PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 CLK
2 SDI
3 SDO
4 GND
5 VSS
6 V1
7 W1
8 B1
9 B2
10 W2
11 V2
12 VDD
13 WP
14 PR
15 CS
16 RDY
Serial Input Register Clock Pin. Shifts in
one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at
a time on positive clock CLK edges.
MSB loaded first.
Serial Data Output Pin. Open-drain out put
requires external pull-up resistor. CMD_9
and CMD_10 activate the SDO output. See
Instruction Operation Truth Table (Table II).
Other commands shift out the previously
loaded SDI bit pattern delayed by 24 clock
pulses. This allows daisy-chain operation of
multiple packages.
Ground Pin, logic ground reference
Negative Supply. Connect to zero volts for
single-supply applications.
Log Output Voltage 1 generated from internal
diode configured transistor
Wiper terminal of RDAC1. ADDR
(RDAC1) = 0H.
B terminal of RDAC1
B terminal of RDAC2
Wiper terminal of RDAC2. ADDR
(RDAC2) = 1H.
Log Output Voltage 2 generated from internal
diode configured transistor
Positive Power Supply Pin
Write Protect Pin. When active low, WP prevents
any changes to the present contents except PR
and CMD_1 and CMD_8 will refresh the
RDAC register from EEMEM. Execute a NOP
instruction before returning to WP high.
Hardware Override Preset Pin. Refreshes the
scratch pad register with current contents of
the EEMEM register. Factory default loads
midscale 51210 until EEMEM loaded with a
new value by the user (PR is activated at the
logic high transition).
Serial Register chip select active low. Serial
register operation takes place when CS returns
to logic high.
Ready. Active high open-drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and PR.
–6–
REV. B
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