ADN2850(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADN2850 Datasheet PDF : 20 Pages
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ADN2850
Table I. 24-Bit Serial Data-Word
MSB Instruction Byte 0
Data Byte 1
Data Byte 0
LSB
RDAC C3 C2 C1 C0 0 0 0 A0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Command bits are C0 to C3. Address bits are A3–A0. Data bits D0 to D9 are applicable to RDAC wiper register whereas D0 to D15 are applicable to EEMEM
Register. Command instruction codes are defined in Table II.
Table II. Instruction Operation Truth Table1, 2, 3
Inst
Instruction Byte 0
Data Byte 1 Data Byte 0 Operation
Number B23 • • • • • • • • • • • • • • • • B16 B15 • • • • • • B8 B7 • • • • • B0
C3 C2 C1 C0 A3 A2 A1 A0 X • • • • D9 D8 D7 • • • • • D0
0
0 0 0 0 X X X X X••••XX
X • • • • • • X NOP: Do nothing. See Table XI for Programming
example.
1
0 0 0 1 0 0 0 A0 X • • • • X X
X • • • • • • X Retrieve contents of EEMEM(A0) to RDAC(A0)
Register. This command leaves device in the Read
Program power state. To return part to the idle state,
perform NOP instruction 0. See Table XI.
2
0 0 1 0 0 0 0 A0 X • • • • X X
X • • • • • • X SAVE WIPER SETTING: Write contents of RDAC(A0)
to EEMEM(A0). See Table X.
34
0 0 1 1 A3 A2 A1 A0 D15 • • • • D8 D7 • • • • • D0 Write contents of Serial Register Data Bytes 0 and
1 (total 16-bit) to EEMEM(ADDR). See Table XIII.
45
0 1 0 0 0 0 0 A0 X • • • • X X
X • • • • • • X Decrement 6 dB: Right shift contents of RDAC(A0)
Register, stops at all “Zeros.”
55
0 1 0 1 X X X X X••••XX
X • • • • • • X Decrement All 6 dB: Right shift contents of all RDAC
Registers, stops at all “Zeros.”
65
0 1 1 0 0 0 0 A0 X • • • • X X
X • • • • • • X Decrement contents of RDAC(A0) by “One,” stops
at all “Zeros.”
75
0 1 1 1 X X X X X••••XX
X • • • • • • X Decrement contents of all RDAC Registers by
“One,” stops at all “Zeros.”
8
1 0 0 0 X X X X X••••XX
X • • • • • • X RESET: Load all RDACs with their corresponding
EEMEM previously saved values.
9
1 0 0 1 A3 A2 A1 A0 X • • • • X X
X • • • • • • X Transfer contents of EEMEM (ADDR) to Serial
Register Data Bytes 0 and 1, and previously stored
data can be read out from the SDO pin. See Table XIV.
10
1 0 1 0 0 0 0 A0 X • • • • X X
X • • • • • • X Transfer contents of RDAC (A0) to Serial Register
Data Bytes 0 and 1, and wiper setting can be read
from the SDO pin. See Table XV.
11
1 0 1 1 0 0 0 A0 X • • • • D9 D8 D7 • • • • • D0 Write contents of Serial Register Data Bytes 0 and
1 (total 11-bit) to RDAC(A0). See Table IX.
125
1 1 0 0 0 0 0 A0 X • • • • X X
X • • • • • • X Increment 6 dB: Left shift contents of RDAC(A0),
stops at all “Ones.” See Table XII.
135
1 1 0 1 X X X X X••••XX
X • • • • • • X Increment All 6 dB: Left shift contents of all RDAC
Registers, stops at all “Ones.”
145
1 1 1 0 0 0 0 A0 X • • • • X X
X • • • • • • X Increment contents of RDAC(A0) by “One,” stops
at all “Ones.” See Table X.
155
1 1 1 1 X X X X X••••XX
X • • • • • • X Increment contents of all RDAC Registers by “One,”
stops at all “Ones.”
NOTES
1The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or 10,
the selected internal register data will be present in data byte 0 and 1. The instructions following 9 and 10 must also be a full 24-bit data-word to completely clock out
the contents of the serial register.
2The RDAC register is a volatile scratch pad register that is refreshed at power ON from the corresponding nonvolatile EEMEM register.
3Execution of the above operations takes place when the CS strobe returns to logic high.
4Instruction 3 writes 2 data bytes (total 16-bit) to EEMEM. But in the cases of addresses 0 and 1, only the last 10 bits are valid for wiper position setting.
5The increment, decrement, and shift commands ignore the contents of the shift register data bytes 0 and 1.
REV. B
–7–
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