ADN2850(RevB) Просмотр технического описания (PDF) - Analog Devices
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ADN2850 Datasheet PDF : 20 Pages
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ADN2850
The output voltage represents the average incoming optical power.
The output voltage of the log stage does not have to be accurate
from device to device, as the responsivity of the photodiode will
change between devices. An op amp stage is shown after the log
amp stage, which compensates for VT variation over temperature.
Equation 4 is ideal. If the reference current is 1 mA at room
temperature, characterization shows that there is an additional
30 mV offset between V2 and V1. A curve fit approximation yields
V2
— V1
= 0.026
×
In
0.001
IPD
+
0.03
(5)
Such offset is believed to be caused by the transistors self-heating
and the thermal gradient effect. As seen in Figure 13, the error
between an approximation and the actual performance ranges is
less than 0% to –4% from 0.1 mA to 0.1 A.
0.30
0.25
0.20
DEVICE 1
DEVICE 2
DEVICE 3
CURVE FIT
12
IREF = 1mA
TA = 25؇C
9
ERROR
6
0.15
3
0.10
0
B1 W1 B2 W2
Figure 14. Reduce Resistance by Half with Linear
Adjustment Characteristics
Much lower resistance can also be achieved by paralleling a
discrete resistor as shown in Figure 15.
W1
B1
R
Figure 15. Resistor Scaling with Pseudo-Log Taper
Adjustment Characteristics
The equivalent resistance at a given setting is approximated as:
Req =
D × RWB_FS + 51200
D × RWB _ FS + 51200 + 1024 × R
(6)
In this approach, the adjustment is not linear but pseudo-
logarithmic. Users should be aware of the need for tolerance matching
as well as temperature coefficient matching of the components.
0.05
–3
BASIC RDAC SPICE MODEL
0
1.E-07
1.E-06
1.E-05
IPD – A
1.E-04
–6
1.E-03
Figure 13. Typical V2 – V1 vs. IPD at IREF = 1 mA
and TA = 25°C
Resistance Scaling
The ADN2850 offers either 25 kΩ or 250 kΩ full-scale resistance.
Users who need lower resistance and still maintain the numbers
of step adjustment can parallel two or more devices. Figure 14
shows a simple scheme of paralleling both channels of the pro-
grammable resistors. In order to adjust half of the resistance
linearly per step, users need to program both devices coherently
with the same settings. Note that since the devices will be pro-
grammed one after another, an intermediate state will occur, and
this method may not be suitable for certain applications.
RDAC
25k⍀
CW = 80pF
B
CB = 11pF
W
Figure 16. RDAC Circuit Simulation Model (RDAC = 25 kΩ)
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RADCs. A general
parasitic simulation model is shown in Figure 16.
Listing I provides a macro model net list for the 25 kΩ RDAC:
Listing I. Macro Model Net List for RDAC
.PARAM D = 1024, RDAC = 25E3
*
.SUBCKT RDAC (W, B)
*
RWB W B {D/1024 ϫ RDAC ϩ 50}
CW W 0 80E-12
CB B 0 11E-12
*
.ENDS RDAC
REV. B
–17–
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