ADN2814(RevPrA) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADN2814
(Rev.:RevPrA)

Continuous Rate 12.3 Mb/s to 675 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

ADN2814

Preliminary Technical Data

I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION

SLAVE ADDRESS [6...0]

R/W

CTRL.

1

A5

0

0

0

0

0

X

MSB = 1 SET BY

PIN 19

0 = WR

1 = RD

Figure 6. Slave Address Configuration

S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)

Figure 7. I2C Write Data Transfer

DATA A(S) P

S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M)

DATA A(M) P

S = START BIT

A(S) = ACKNOWLEDGE BY SLAVE

P = STOP BIT

A(M) = LACK OF ACKNOWLEDGE BY MASTER

A(M) = ACKNOWLEDGE BY MASTER

Figure 8. I2C Read Data Transfer

START BIT

SDA

SLAVE ADDRESS

A6

A5

SCK

S

SLADDR[4...0]

SUB ADDRESS

A7

A0

DATA

D7

D0

STOP BIT

WR ACK

SUB ADDR[6...1]

ACK

Figure 9. I2C Data Transfer Timing

DATA[6...1]

ACK

P

tF

SDA

SCK

S

tSU;DAT

tHD;STA

tR

tF

tLOW

tSU;STO

tHD;STA

tHD;DAT

tHIGH tSU;STA

S

Figure 10. I2C Port Timing Diagram

tBUF

tR

P

S

Rev. PrA | Page 10 of 28

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