ADN2811(RevA) Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
ADN2811
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADN2811 Datasheet PDF : 16 Pages
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PIN CONFIGURATION
ADN2811
THRADJ 1
VCC 2
VEE 3
VREF 4
PIN 5
NIN 6
SLICEP 7
SLICEN 8
VEE 9
LOL 10
XO1 11
XO2 12
PIN 1
INDICATOR
ADN2811
TOP VIEW
NC = NO CONNECT
36 VCC
35 VCC
34 VEE
33 VEE
32 NC
31 NC
30 RATE
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2
PIN FUNCTION DESCRIPTION
Pin No.
1
2, 26, 28, Pad
3, 9, 16, 19, 22, 27, 29,
33, 34, 42, 43, 46
4
5
6
7
8
10
11
12
13
Mnemonic
THRADJ
VCC
VEE
VREF
PIN
NIN
SLICEP
SLICEN
LOL
XO1
XO2
REFCLKN
14
REFCLKP
15
REFSEL
17
18
20, 47
21
23
24
25
30
31, 32
35, 36
37
38
39
40
41
44
45
48
TDINP
TDINN
VCC
CF1
REFSEL1
REFSEL0
CF2
RATE
NC
VCC
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
BYPASS
SDOUT
LOOPEN
Type
AI
P
P
AO
AI
AI
AI
AI
DO
AO
AO
DI
DI
DI
AI
AI
P
AO
DI
DI
AO
DI
DI
P
DO
DO
DI
DO
DO
DI
DO
DI
Description
LOS Threshold Setting Resistor
Analog Supply
Ground
Internal VREF Voltage. Decouple to GND with 0.1 µF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
Differential Slice Level Adjust Input
Differential Slice Level Adjust Input
Loss of Lock Indicator. LVTTL active high.
Crystal Oscillator
Crystal Oscillator
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS
(LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. “0” = on-chip oscillator with external crystal;
“1” = external clock source, LVTTL.
Differential Test Data Input
Differential Test Data Input
Digital Supply
Frequency Loop Capacitor
Reference Frequency Select (See Table II) LVTTL.
Reference Frequency Select (See Table II) LVTTL.
Frequency Loop Capacitor
Data Rate Select (See Table I) LVTTL.
No Connect
Output Driver Supply
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss of Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
REV. A
–5–
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