ADN2807(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADN2807
(Rev.:RevA)

155/622 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp

Analog Devices 

LOS RESPONSE TIME

The LOS response time is the delay between the removal of the

input signal and indication of loss of signal (LOS) at SDOUT.

The ADN2807’s response time is 300 ns typ when the inputs are

dc-coupled. In practice, the time constant of ac coupling at the

quantizer input determines the LOS response time.

JITTER SPECIFICATIONS

The ADN2807 CDR is designed to achieve the best bit-error-

rate (BER) performance, and has exceeded the jitter transfer,

generation, and tolerance specifications proposed for

SONET/SDH equipment defined in the Telcordia Technologies

specification. Jitter is the dynamic displacement of digital signal

edges from their long-term average positions measured in UI

(unit intervals), where 1 UI = 1 bit period. Jitter on the input

data can cause dynamic phase errors on the recovered clock

sampling edge. Jitter on the recovered clock causes jitter on the

retimed data. The following sections briefly summarize the

specifications of the jitter generation, transfer, and tolerance in

accordance with the Telcordia document (GR-253-CORE, Issue

3, September 2000) for the optical interface at the equipment

level, and the ADN2807 performance with respect to those

specifications.

Jitter Generation

The jitter generation specification limits the amount of jitter

that can be generated by the device with no jitter and wander

applied at the input.

Jitter Transfer

The jitter transfer function is the ratio of the jitter on the output

signal to the jitter applied on the input signal versus the

frequency. This parameter measures the limited amount of jitter

on an input signal that can be transferred to the output signal

(Figure 11).

0.1

ACCEPTABLE

RANGE

ADN2807

SLOPE = –20dB/DECADE

fC

JITTER FREQUENCY (kHz)

Figure 11. Jitter Transfer Curve

Jitter Tolerance

The jitter tolerance is defined as the peak-to-peak amplitude of

the sinusoidal jitter applied on the input signal that causes a

1 dB power penalty. This is a stress test intended to ensure that

no additional penalty is incurred under the operating

conditions (Figure 12).

15

SLOPE = –20dB/DECADE

1.5

0.15

f0

f1

f2 f3

f4

JITTER FREQUENCY (Hz)

Figure 12. SONET Jitter Tolerance Mask

Table 4. Jitter Transfer and Tolerance: SONET Specifications vs. ADN2807

Jitter Transfer

Jitter Tolerance

SONET ADN2807 Implementation Mask Corner

SONET Spec ADN2807

Rate Spec (fC) (kHz)

Margin

Frequency (kHz) ADN2807 (UI p-p)

(UI p-p)

OC-12 500 kHz 140

3.6

250 kHz

4.8 MHz 0.15

1.0

OC-3 130 kHz 48

2.7

65 kHz

600 kHz 0.15

1.0

Implementation

Margin2

6.67

6.67

2 Jitter tolerance measurements are limited by test equipment capabilities.

Rev. A | Page 9 of 20

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