ADN2805(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADN2805 Datasheet PDF : 16 Pages
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADN2805
TEST1 1
VCC 2
VREF 3
NIN 4
PIN 5
NC 6
NC 7
VEE 8
PIN 1
INDIC ATOR
ADN2805*
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1
TEST1
2
VCC
3
VREF
4
NIN
5
PIN
6, 7, 9, 22
NC
8
VEE
10
REFCLKP
11
REFCLKN
12
VCC
13
VEE
14
CF2
15
CF1
16
LOL
17
VEE
18
VCC
19
SADDR5
20
SCK
21
SDA
23
VEE
24
VCC
25
CLKOUTN
26
CLKOUTP
27
SQUELCH
28
DATAOUTN
29
DATAOUTP
30
VEE
31
VCC
32
TEST2
Exposed Pad
Pad
Type 1
P
AO
AI
AI
P
DI
DI
P
P
AO
AO
DO
P
P
DI
DI
DI
P
P
DO
DO
DI
DO
DO
P
P
P
Description
Connect to VCC.
Power for Limiting Amplifier, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
No Connect.
GND for Limiting Amplifier, LOS.
Differential REFCLK Input. 10 MHz to 160 MHz.
Differential REFCLK Input. 10 MHz to 160 MHz.
VCO Power.
VCO GND.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss-of-Lock Indicator. LVTTL active high.
FLL Detector GND.
FLL Detector Power.
Slave Address Bit 5.
I2C Clock Input.
I2C Data Input.
Output Buffer, I2C GND.
Output Buffer, I2C Power.
Differential Recovered Clock Output. LVDS.
Differential Recovered Clock Output. LVDS.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Data Output. LVDS.
Differential Recovered Data Output. LVDS.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Connect to VCC.
Connect to GND.
1 Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. 0 | Page 7 of 16
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