ADN2805(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADN2805 Datasheet PDF : 16 Pages
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ADN2805
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
LVDS OUTPUT CHARACTERISTICS
CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN
Differential Output Swing
Output Offset Voltage
Output Impedance
LVDS Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
I2C® INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Input Low Voltage
Input High Voltage
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Conditions
Min
VOD (see Figure 3)
VOS (see Figure 3)
Differential
20% to 80%
80% to 20%
TS (see Figure 2), GbE
TH (see Figure 2), GbE
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 10
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tR/tF
tSU;STO
tBUF
Optional lock-to-REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
240
1125
360
360
0.7 VCC
−10.0
600
1300
600
600
100
300
20 + 0.1 Cb1
600
1300
10
VIH
2.0
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
−5
VOH, IOH = −2.0 mA
2.4
VOL, IOL = 2.0 mA
1 Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed.
Typ Max
300
1200
100
400
1275
115 220
115 220
400 440
400 440
0.3 VCC
+10.0
0.4
400
300
0
VCC
100
160
100
0.8
5
0.4
Unit
mV
mV
Ω
ps
ps
ps
ps
V
V
μA
V
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
mV p-p
MHz
ppm
V
V
μA
μA
V
V
Rev. 0 | Page 4 of 16
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