ADMCF340
TIMING PARAMETERS
Parameter
Clock Signals
Signal TCK is defined as 0.5 tCKIN. The ADMCF340 uses an input clock with
a frequency equal to half the instruction rate; a 10 MHz input clock (which is
equivalent to 100 ns) yields a 50 ns processor cycle (equivalent to 20 MHz).
When TCK values are within the range of 0.5 tCKIN period, they should be
substituted for all relevant timing parameters to obtain specification value as
in the following example:
tCKH = 0.5 TCK − 10 ns = 0.5 × 50 ns − 10 ns = 15 ns
Timing Requirements:
tCKIN
CLKIN Period
tCKIL
CLKIN Width Low
tCKIH
CLKIN Width High
Switching Characteristics:
tCKL
tCKH
tCKOH
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
Control Signals
Timing Requirement:
tRSP
RESET Width Low
PWM Shutdown Signals
Timing Requirement:
tPWMTPW PWMTRIP Width Low
*Applies after power-up sequence is complete.
Specifications subject to change without notice.
Min
100
20
20
0.5 TCK – 10
0.5 TCK – 10
0
5 TCK*
TCK
Max
150
20
CLKIN
CLKOUT
tCKIN
tCKIH
tCKIL
tCKOH
tCKH
tCKL
Figure 1. Clock Signals
Unit
ns
ns
ns
ns
ns
ns
ns
ns
–4–
REV. 0