ADMCF340 Просмотр технического описания (PDF) - Analog Devices
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ADMCF340 Datasheet PDF : 40 Pages
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ADMCF340
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data-word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has one pin, SCLK0, shared with SPORT1. Dur-
ing a boot phase (SPORT1 Boot Mode enabled by a bit in
the MODECTRL Register), the serial clock of SPORT1 is
externally available. The serial clock of SPORT0 is exter-
nally available when the SPORT1 is configured in UART
Mode.
• SPORT0 can be configured as SPI port (master mode only).
Refer to Table XI for more information. The clock phase and
polarity are programmable through the MODECTRL Register.
Refer to Table XI for pin configuration.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24-word or 32-word time division multiplexed
serial bitstream.
• SPORT1 is the default port for program/data memory boot
loading and for the development tools interface. The DT1/FL1
Pin can be configured as the SROM/E2 prom reset signal.
The ADMCF340 is available in a 64-lead LQFP package.
PIN FUNCTION DESCRIPTION
Table I. Pin List
Pin Group
Name
# of Input/
Pins Output Function
PWMPOL
PWMSR
RESET
SPORT11
SPORT01
1I
1I
1I
2 I/O
5 I/O
CLKOUT1
CLKIN, XTAL
11 I/O
2 I/O
PORTA0–PORTA81 9 I/O
PORTB0–PORTB15 16 I/O
AUX0–AUX11
2O
AH-CL
6O
PWMTRIP
1I
V1 to V3
3I
ISENSE1 to ISENSE3
3I
VAUX0-VAUX7 7 I
ICONST
1O
VDD
GND
3I
3I
PWM Polarity
PWM Switched
Reluctance Mode
Processor Reset Input
Serial Port 1 Pins
(DT1/FL1, DR1)
Serial Port 0 Pins
(DT0, DR0, RFS0,
TFS0, SCLK1/
SCLK02)
Processor Clock
Output
External Clock or
Quart Crystal
Connection Point
Digital I/O Port Pins
Digital I/O Port Pins
Auxiliary PWM
Outputs
PWM Outputs
PWM Trip Signal
ISENSE Inputs
Analog Inputs
Auxiliary Analog Inputs
ADC Constant
Current Source
Power Supply
Ground
NOTES
1Multiplexed pins, individually selectable through PORTA_SELECT and
PORTA_DATA Registers.
2SCLK1/SCLK0 multiplexed signals. Selectable through MODECTRL
Register Bit 4.
INTERRUPT OVERVIEW
The ADMCF340 can respond to 34 different interrupt sources
with minimal overhead, seven of which are internal DSP core
interrupts and 27 are from the motor control peripherals. The seven
DSP core interrupts are SPORT1 receive (or IRQ0) and transmit
(or IRQ1), SPORT0 receive and transmit, the internal timer,
and two software interrupts. The motor control peripheral
interrupts are the 25 programmable I/Os and two from the PWM
(PWMSYNC pulse and PWMTRIP). All motor control interrupts
are multiplexed into the DSP core through the peripheral IRQ2
interrupt. The interrupts are internally prioritized and individually
maskable. A detailed description of the entire interrupt system of
the ADMCF340 is presented later, following a more detailed
description of each peripheral block.
MEMORY MAP
The ADMCF340 has two distinct memory types: program
and data. In general, program memory contains user code and
coefficients, while the data memory is used to store variables and
data during program execution. Three kinds of program memory are
provided on the ADMCF340: RAM, ROM, and FLASH. The
motor control peripherals are memory mapped into a region of the
data memory space starting at 0x2000. The complete program and
data memory maps are given in Tables II and III, respectively.
Table II. Program Memory Map
Address Range
Memory
Type
Function
0x0000–0x002F
0x0030–0x01FF
0x0200–0x07FF
0x0800–0x17FF
0x1800–0x1FFF
0x2000–0x20FF
0x2100–0x21FF
0x2200–0x2FFF
0x3000–0x3FFF
RAM
RAM
ROM
FLASH
FLASH
FLASH
Internal Vector Table
User Program Memory
Reserved
Reserved Program Memory
Reserved
User Program Memory
Sector 0
User Program Memory
Sector 1
User Program Memory
Sector 2
Reserved
Table III. Data Memory Map
Address Range
0x0000–0x1FFF
0x2000–0x20FF
0x2100–0x37FF
0x3800–0x39FF
0x3A00–0x3BFF
0x3C00–0x3FFF
Memory
Type
RAM
RAM
Function
Reserved
Memory Mapped Registers
Reserved
User Data Memory
Reserved
Memory Mapped Registers
–10–
REV. 0
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