ADM8840 Просмотр технического описания (PDF) - Analog Devices

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ADM8840

Charge Pump Regulator & COM Driver for Color TFT Panel

Analog Devices 

PRELIMINARY TECHNICAL DATA

SERIAL INTERFACE

The COM Driver section of the ADM8840 uses a serial

interface to input data and transfer it into the DACs. Figure

3, below, shows the operation of the serial interface. The data

is transmitted along the serial DATA line, along with a serial

clock signal, SCLK. This data is read into a Shift Register.

When the 8 bits are sucessfully stored in the Shift Register a

low-to-high transition on the CS/LDAC input causes the

latch to load the 8-bits of data into the relevent DAC.

This function is also shown in the waveforms in Figure 4

below. A falling edge on the CS/LDAC input initiates the

data read into the shift register. The first bit of the datastream

is the DAC Select Bit (DAC_SEL) which determines which

internal DAC the data will be written to. A ‘1’ selects DAC

1 which sets the Amplitude of the output and a ‘0’ selects

ADM8840

DAC 2 which sets the Centre Voltage of the output. The

individual data bits are then read in one by one on the DATA

line. After the DAC_SEL bit and the 8 data bits have been

read there is a pause to ensure the shift register outputs are

stable. Then a rising edge on the CS/LDAC input loads the

8 bits on the shift register outputs into the relevent DAC (and

the DAC outputs will change accordingly). Note that if CS/

LDAC goes high before all 8 data bits are read in then

incorrect data will be loaded into the DACs. All bits on the

DATA line are read in on each rising edge of the SCLK

signal.

When the ADM8840 comes out of shutdown the DACs

are preset with default values generating a COM_OUT

Amplitude of 6V with a Centre voltage of 1.5V.

DATA

SHIFT

REGISTER

8 DATA BITS

DAC 1

LATCH

SCLK

DAC_SEL BIT

DAC

SELECT

DAC 2

LATCH

DAC 1

(AMPLITUDE)

DAC 1 OUT

DAC 2

(CENTRE VOLTAGE)

DAC 2 OUT

CS/LDAC

Figure 3. Serial Interface Diagram

t1

CS / LDAC

t4

t3

t2

SCLK

DATA

D AC

SEL

D0

D1 D2

D3 D4

D5 D6 D7

REV. PrG 2/03

t7

t6

t5

Figure 4. Serial Interface Waveforms

–7–

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