ADM8694AN Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADM8694AN

Microprocessor Supervisory Circuits

Analog Devices 

ADM8690–ADM8695

CE Gating and RAM Write Protection (ADM8691/ADM8693/

ADM8695)

The ADM8691/ADM8693/ADM8695 products include

memory protection circuitry which ensures the integrity of data

in memory by preventing write operations when VCC is at an in-

valid level. There are two additional pins, CEIN and CEOUT,

which may be used to control the Chip Enable or Write inputs

of CMOS RAM. When VCC is present, CEOUT is a buffered rep-

lica of CEIN, with a 3 ns propagation delay. When VCC falls be-

low the reset voltage threshold or VBATT, an internal gate forces

CEOUT high, independent of CEIN.

CEOUT typically drives the CE, CS or write input of battery

backed up CMOS RAM. This ensures the integrity of the data

in memory by preventing write operations when VCC is at an in-

valid level. Similar protection of EEPROMs can be achieved by

using the CEOUT to drive the store or write inputs.

(PFI) is compared to an internal +1.3 V reference. The Power

Fail Output (PFO) goes low when the voltage at PFI is less than

1.3 V. Typically PFI is driven by an external voltage divider that

senses either the unregulated dc input to the system’s 5 V regu-

lator or the regulated 5 V output. The voltage divider ratio can

be chosen such that the voltage at PFI falls below 1.3 V several

milliseconds before the +5 V power supply falls below the reset

threshold. PFO is normally used to interrupt the microprocessor

so that data can be stored in RAM and the shut down procedure

executed before power is lost

INPUT

POWER

R1

R2

POWER

FAIL

INPUT

ADM869x

1.3V

PFO

POWER

FAIL

OUTPUT

CEIN

ADM869x

VCC LOW = 0

VCC OK = 1

CEOUT

Figure 5. Chip Enable Gating

VCC

V2

V1

V2

V1

RESET

t1

t1

LOW LINE

CEIN

CEOUT

t1 = RESET TIME

V1 = RESET VOLTAGE THRESHOLD LOW

V2 = RESET VOLTAGE THRESHOLD HIGH

HYSTERESIS = V2–V1

Figure 6. Chip Enable Timing

Power Fail Warning Comparator

An additional comparator is provided for early warning of fail-

ure in the microprocessor’s power supply. The Power Fail Input

Figure 7. Power Fail Comparator

Table II. Input and Output Status In Battery Backup Mode

Signal

VOUT

RESET

RESET

LOW LINE

BATT ON

WDI

WDO

PFI

PFO

CEIN

CEOUT

OSC IN

OSC SEL

Status

VOUT is connected to VBATT via an internal

PMOS switch.

Logic low.

Logic high. The open circuit output voltage is

equal to VOUT.

Logic low.

Logic high. The open circuit voltage is equal to

VOUT.

WDI is ignored. It is internally disconnected

from the internal pull-up resistor and does not

source or sink current as long as its input voltage

is between GND and VOUT. The input voltage

does not affect supply current.

Logic high. The open circuit voltage is equal

to VOUT.

The Power Fail Comparator is turned off and

has no effect on the Power Fail Output.

Logic low.

CEIN is ignored. It is internally disconnected

from its internal pull-up and does not source or

sink current as long as its input voltage is

between GND and VOUT. The input voltage

does not affect supply current.

Logic high. The open circuit voltage is equal to

VOUT.

OSC IN is ignored.

OSC SEL is ignored.

–8–

REV. 0

Share Link: