ADM6384 Просмотр технического описания (PDF) - Analog Devices

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ADM6384

Microprocessor Supervisory Circuit in 4-Lead SC70

Analog Devices 

CIRCUIT DESCRIPTION

The ADM6384 provides microprocessor supply voltage supervi-

sion by controlling the microprocessor reset input. Code execution

errors are avoided during power-up, power-down, and brownout

conditions by asserting a reset signal when the supply voltage is

below a preset threshold. In addition, the ADM6384 allows

supply voltage stabilization with a fixed timeout before the reset

deasserts after the supply voltage rises above the threshold. If the

user detects a problem with the system operation, a manual reset

input is available to reset the microprocessor by means of an

external push-button, for example.

RESET OUTPUT

The ADM6384 features an active-low, push-pull reset output.

The reset signal is guaranteed to be logic low for VCC down to 1 V.

The reset output is asserted when VCC is below the reset threshold

(VTH) or when MR is driven low. Reset remains asserted for the

duration of the reset active timeout period (tRP) after VCC rises

above the reset threshold or after MR transitions from low to high.

Figure 12 illustrates the behavior of the reset outputs.

ADM6384

VCC

VCC

VTH

VTH

1V

0V

VCC

RESET

tRP

tRD

0V

Figure 12. Reset Timing Diagram

MANUAL RESET INPUT

The ADM6384 features a manual reset input (MR) that, when

driven low, asserts the reset output. When MR transitions from

low to high, reset remains asserted for the duration of the reset

active timeout period before deasserting. The MR input has a

52 kΩ internal pull-up so that the input is always high when

unconnected. An external push-button switch can be connected

between MR and ground so that the user can generate a reset.

Debounce circuitry for this purpose is integrated on-chip. Noise

immunity is provided on the MR input, and fast, negative-going

transients of up to 100 ns (typical) are ignored. A 0.1 µF capacitor

between MR and ground provides additional noise immunity.

Rev. C | Page 9 of 12

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