CAT28LV65 Просмотр технического описания (PDF) - Catalyst Semiconductor => Onsemi
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CAT28LV65 Datasheet PDF : 12 Pages
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Figure 1. A.C. Testing Input/Output Waveform(4)
VCC - 0.3 V
0.0 V
INPUT PULSE LEVELS
2.0 V
0.6 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
Vcc
DEVICE
UNDER
TEST
1. 3K
1.8 K
OUTPUT
CL= 100 pF
CAT28LV65
CL INCLUDES JIG CAPACITANCE
A.C. CHARACTERISTICS, Write Cycle
Vcc = 3.0V to 3.6V, unless otherwise specified.
28LV65-15
28LV65-20
28LV65-25
Symbol Parameter
Min
Max
Min
Max Min Max Units
tWC
Write Cycle Time
5
5
5
ms
tAS
Address Setup Time0
0
0
0
ns
tAH
Address Hold Time
100
100
100
ns
tCS
CE Setup Time
0
0
0
ns
tCH
CE Hold Time
0
0
0
ns
tCW(2) CE Pulse Time
110
150
150
ns
tOES
OE Setup Time
0
10
10
ns
tOEH
OE Hold Time
0
10
10
ns
tWP(2) WE Pulse Width
110
150
150
ns
tDS
Data Setup Time
60
100
100
ns
tDH
Data Hold Time
0
0
0
ns
tINIT(1)
Write Inhibit Period
After Power-up
5
10
5
10
5
10
ms
tBLC(1)(3) Byte Load Cycle Time
0.05
100
0.1
100 0.1 100
µs
tRB
WE Low to RDY/Busy Low
220
220
220
ns
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
(4) Input rise and fall times (10% and 90%) < 10 ns.
5
Doc. No. 1024, Rev. D
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