ADM1487AR Просмотр технического описания (PDF) - Analog Devices
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производитель
ADM1487AR
Analog Devices
ADM1487AR Datasheet PDF : 8 Pages
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ADM1487
ADM1487 TEST CIRCUITS AND TIMING
A
R
VOD
R
A
VOC
OUTPUT
UNDER
TEST
Figure 1. Driver DC Load Test Circuit
VCC
TEST
POINT
S1
500V
CRL
S2
15pF
3V
DE
A
A
CL1
DI
D
VOD2
RDIFF
R
RO
B
B
CL2
15pF
Figure 2. Driver/Receiver Timing Test Circuit
3V
DI
0V
B
A
V0
VDIFF 0V
-V0
1.5V
f = 1MHz, tr # 10ns, tf # 10ns
tDPLH
tDPHL
V0
V0/2
10%
90%
VDIFF = VA - VB
90%
tDR
tDF
tSKEW = |tDPLH-tDPHL|
10%
Figure 3. Driver Propagation Delays
A VOD2
f = 1MHz, tr # 10ns, tf # 10ns
B -VOD2
VOH
RO
VOL
tRPHL
tRPLH
1.5V
Figure 4. Receiver Propagation Delays
Figure 5. Test Load for Driver Enable/Disable Time Test
3V
DE
0V
5V
A, B
VOL
VOH
A, B
VOL
f = 1MHz, tr # 10ns, tf # 10ns
1.5V
tDZL(SHDN), tDZL
tDLZ
2.3V
OUTPUT NORMALLY LOW
VOL+ 0.5V
OUTPUT NORMALLY HIGH
2.3
VOH- 0.5V
VtDZH(SHDN), tDZH
tDHZ
Figure 6. Driver Enable and Disable Times
VCC
1kV
TEST
POINT
S1
RO
CRL
15pF
S2
1kV
Figure 7. Test Load for Receiver Enable/Disable Time Test
3V
RE
0V
5V
RO
f = 1MHz, tr # 10ns, tf # 10ns
tRZL(SHDN), tRZL
tRLZ
1.5
OUTPUT NORMALLY LOW
V
1.5
V
0.5V
5V
RO
0V
OUTPUT NORMALLY HIGH
1.5
VtRZH(SHDN), tRZH
tRHZ
0.5V
Figure 8. Receiver Enable and Disable Delay Times
Rev. PrC
–5–
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