ADM1178 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADM1178

Hot Swap Controller and Digital Power Monitor with ALERTB Output

Analog Devices 

ADM1178

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Data Sheet

VCC 1

SENSE 2

ON 3

GND 4

TIMER 5

10 ALERTB

ADM1178

TOP VIEW

(Not to Scale)

9 GATE

8 ADR

7 SDA

6 SCL

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic

Description

1

VCC

Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 16.5 V. An undervoltage

lockout (UVLO) circuit resets the ADM1178 when a low supply voltage is detected.

2

SENSE

Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin sets the analog current

limit. The hot swap operation of the ADM1178 controls the external FET gate to maintain the (VCC − VSENSE)

voltage at or below 100 mV.

3

ON

Undervoltage Input Pin. Active high pin. An internal undervoltage comparator has a trip threshold of 1.3 V,

and the output of this comparator is used as an enable for the hot swap operation. With an external resistor

divider from VCC to GND, the ON pin can be used to enable the hot swap operation for a specific voltage on

VCC, providing an undervoltage function.

4

GND

Chip Ground Pin.

5

TIMER

Timer Pin. An external capacitor, CTIMER, sets a 270 ms/µF initial timing cycle delay and a 21.7 ms/µF fault delay.

The GATE pin turns off when the TIMER pin is pulled beyond the upper threshold. An overvoltage detection

with an external Zener can be used to force this pin high.

6

SCL

I2C Clock Pin. Open-drain input requires an external resistive pull-up.

7

SDA

I2C Data I/O Pin. Open-drain input/output. Requires an external resistive pull-up.

8

ADR

I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor to set four I2C

addresses.

9

GATE

GATE Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the

FET drive controller, which utilizes a charge pump to provide a 12.5 µA pull-up current to charge the FET

GATE pin. The FET drive controller regulates to a maximum load current (100 mV through the sense resistor)

by modulating the GATE pin.

10

ALERTB

Alert Output Pin. Active low, open-drain configuration. This pin asserts when an overcurrent condition is

present. The overcurrent level that causes an alert to be asserted is digitally programmable via the I2C

interface. This function can also be enabled/disabled via I2C.

Rev. D | Page 6 of 24

Share Link: