ADM1041AARQZ Просмотр технического описания (PDF) - Analog Devices

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ADM1041AARQZ

Secondary-Side Controller with Current Share and Housekeeping

Analog Devices 

ADM1041A

TEST NAME TABLE

This table is an ADI internal reference. It is a cross reference for the ADI test program.

Table 44.

Specification

Supplies

VDD

IDD, Current Consumption

Peak IDD, during EEPROM Erase Cycle

UNDERVOLTAGE LOCKOUT, VDD

Start-Up Threshold

Stop Threshold

Hysteresis

POWER BLOCK PROTECTION

VDD Overvoltage

VDD Overvoltage Debounce

Open Ground

Debounce

POWER-ON RESET

DC Level

DIFFERENTIAL LOAD VOLTAGE SENSE I

VS− Input Voltage

VS+ Input Voltage

VS− Input Resistance

VS+ Input Resistance

VNOM Adjustment Range

Set Load Voltage Trim Step

Minimum Set Load Overvoltage Trim

Range

Set Load Overvoltage Trim Step

Recover Load OV False to FG True

Time from Load OV to FG False

LOCAL VOLTAGE SENSE, VLS, AND

FALSE UNDERVOLTAGE CLAMP

Input Voltage Range

Stage Gain

False UV Clamp, VLS Input Voltage

Nominal, and Trim Range

Clamp Trim Step

LOCAL OVERVOLTAGE

Nominal and Trim Range

OV Trim Step

OV Trim Step

Noise Filter, for OVP Function Only

LOCAL UNDERVOLTAGE

UV Trim Step

UV Trim Step

Noise Filter, for UVP Function Only

VOLTAGE ERROR AMPLIFIER

Reference Voltage

Temperature Coefficient

Long-Term Voltage Stability

Soft-Start Period Range

Test Name

VDD

IDD

VDD (ON)

VDD (OFF)

VDDHYS

VOVP

TDFILTER

VGND

TDEBOUNCE

VPOR

VDVCM

VDVIN_MAX

VDVINRN

VDVINRP

VDVADJ

VDVTRIM

VDVLOV

VLOVTRIM

TLOADOV_FALSE

TLOADOV_TRUE

VLS_RANGE

ACLAMP

VCLMPTRIM

VCLMPSTEP

VLSOV

VLSOVSTEP

VLSOVSTEP

TNFOVP

VLSUV

VLSUVSTEP

VLSUVSTEP

TNFUVP

VCMP

VREF_VCMP

TCV

VSTAB

TSSRANGE

Specification

VOLTAGE ERROR AMPLIFIER (CONT.)

Set Soft-Start Period

Unity Gain Bandwidth

Transconductance

Source Current

Sink Current

DIFFERENTIAL CURRENT-SENSE INPUT,

Cs – Cs+

Common-Mode Range,

External Divider Tolerance Trim

Range (with respect to input)

External Divider Tolerance Trim Step

DC Offset Trim Range (os_dc_range)

DC Offset Trim Step Size

Total Offset Temperature Drift

Gain Range (Isense_range)

Gain Setting 1 (16h, B2–0 = 000)

Gain Setting 2 (16h, B2–0 = 001)

Gain Setting 3 (16h, B2–0 = 010)

Gain Setting 4 (16h, B2–0 = 100)

Gain Setting 5 (16h, B2–0 = 101)

Gain Setting 6 (16h, B2–0 = 110)

CURRENT-SENSE CALIBRATION

Full Scale (No Offset)

Current Share Trim Step (At SHRO),

Cal. Accuracy, 20 mV at CS+, CS−

Cal. Accuracy, 40 mV at CS+, CS–

Cal. Accuracy, 40 mV at CS+, CS−

SHARE BUS OFFSET

Current Share Offset Range

Zero Current Offset Trim Step

CURRENT TRANSFORMER SENSE INPUT

Gain Setting 0

Gain Setting 1

CT Input Sensitivity (Gain Set 0)

CT Input Sensitivity (Gain Set 1)

Input Impedance

Source Current

Source Current Step Size

Reverse Current for Extended SMBus

CURRENT-LIMIT ERROR AMPLIFIER

Current Limit Trim Range

Current Limit Trim Step

Current Limit Trim Step

Transconductance

Output Source Current

Output Sink Current

Test Name

TSS

GBW

G mVCMP

ISOURCE_VCMP

ISINK_VCMP

VCM_RANGE

VOS_DIV_RANGE

VOS_DIV_STEP

VOS_DC_RANGE

VOS_DC_STEP

TDRIFT

Isense_range

G65X

G85X

G110X

G135X

G175X

G230X

VSHR

VSHRSTEP

TolCSHR

TolCSHR

TolCSHR

VZO

VZOSTEP

ICT

GCT_X4

GCT_X2

VCT_X4

VCT_X2

RIN_CT

ISOURCE_CT

ISTEP_CT

IREV

CLIM

CLIMSTEP

CLIMSTEP

GmCCMP

ISOURCE_CCMP

ISINK_CCMP

Rev. 0 | Page 51 of 56

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