ADM1041AARQZ Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
ADM1041AARQZ Datasheet PDF : 56 Pages
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Parameter
OVP Noise Filter
UVP Noise Filter
PSON7
Input Low Level8
Input High Level8
Debounce
PEN7, DC_OK7, CBD, AC_OK
Open-Drain N-Channel Option
Output Low Level = On8
Open-Drain P-Channel
Output High Level = On8
Leakage Current
DC_OK7
DC_OK, On Delay (Power-On and OK Delay)
DC_OK, Off Delay (Power-Off Early Warning)
SMBus, SDL/SCL
Input Voltage Low8
Input Voltage High8
Output Voltage Low8
Pull-Up Current
Leakage Current
ADD0, HARDWIRED ADDRESS BIT
ADD0 Low Level8
ADD0 Floating
ADD0 High8
SERIAL BUS TIMING
Clock Frequency
Glitch Immunity, tSW
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
EEPROM RELIABILITY
Endurance9
Data Retention10
Min
Typ
5
300
2.0
80
0
40
160
2.4
−5
400
200
800
1600
2
0
1
4
2.2
100
−5
VDD/2
VDD − 0.5
4.7
4.7
4
4.7
4
250
300
100
250
100
Max
Unit
25
μs
600
μs
0.8
V
V
ms
ms
ms
ms
ADM1041A
Test Conditions/Comments
Reg 0Fh[4:2] = 010 or 100.
See Table 24.
Reg 0Fh[4:2] = 011 or 101.
See Table 24.
Reg 0Eh[4:2] = 00x. See Table 23.
Reg 0Fh[1:0] = 00. See Table 24.
Reg 0Fh[1:0] = 01. See Table 24.
Reg 0Fh[1:0] = 10. See Table 24.
Reg 0Fh[1:0] = 11. See Table 24.
0.4
+5
0.8
0.4
350
+5
0.4
400
50
1000
300
V
V
μA
ms
ms
ms
ms
ms
ms
ms
ms
V
V
V
μA
μA
V
V
V
kHz
ns
μs
μs
μs
μs
μs
ns
ns
ns
ns
k cycles
Years
ISINK = 4 mA
VOH_PEN
ISOURCE = 4 mA
Reg 0Fh[7:5] = 00x. See Table 24.
Reg 0Eh[1:0] = 00. See Table 23.
Reg 0Eh[1:0] = 01. See Table 23.
Reg 0Eh[1:0] = 10. See Table 23.
Reg 0Eh[1:0] = 11. See Table 23.
Reg 10h[7:6] = 00. See Table 25.
Reg 10h[7:6] = 01. See Table 25.
Reg 10h[7:6] = 10. See Table 25.
Reg 10h[7:6] = 11. See Table 25.
VDD = 5 V, ISINK = 4 mA
Floating
See Figure 5
Rev. 0 | Page 11 of 56
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