ADM1041ARQ-REEL Просмотр технического описания (PDF) - Analog Devices
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производитель
ADM1041ARQ-REEL Datasheet PDF : 64 Pages
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ADM1041
Parameter
Min
Typ
DC Offset Trim Range (with respect to input)
−8
−15
−30
8
15
30
DC Offset Trim Step Size
30
(with respect to input)
50
120
CURRENT SENSE CALIBRATION
Total Current Sense Error2
(Gain and Offset)
±3
±6
Gain Range (ISENSE)
Gain Setting 1 (Reg 16h[2:0] = 000)
65
Gain Setting 2 (Reg 16h[2:0] = 001)
85
Gain Setting 3 (Reg 16h[2:0] = 010)
110
Gain Setting 4 (Reg 16h[2:0] = 100)
135
Gain Setting 5 (Reg 16h[2:0] = 101)
175
Gain Setting 6 (Reg 16h[2:0] = 110)
230
Max
Unit
mV
mV
mV
mV
mV
mV
µV
µV
µV
%
%
V/V
V/V
V/V
V/V
V/V
V/V
Full Scale (No Offset)
Attenuation Range
Current Share Trim Step (at SHRO)
Gain Accuracy2, 4, 40 mV at CS+, CS−
2.0
V
65 to 99
%
0.4
%
8
mV
−5
+5
%
Gain Accuracy2, 4, 20 mV at CS+, CS−
−5
±1
+5
%
Gain Accuracy2, 4, 40 mV at CS+, CS–
−2.5 ±0.5
+2.5
%
SHARE BUS OFFSET
Current Share Offset Range
1.25
V
Zero Current Offset Trim Step
0.4
%
5.5
mV
CURRENT TRANSFORMER SENSE INPUT, ICT
Gain Setting 0
Gain Setting 1
4.5
V/V
2.57
V/V
CT Input Sensitivity
CT Input Sensitivity
Input Impedance2
Source Current
Source Current Step Size
Reverse Current for Extended SMBus
Addressing (Source Current) 5
0.45
0.5
0.79
1.0
20
50
2.0
170
3.5
5
0.68
V
1.20
V
kΩ
µA
nA
7
mA
Rev. A | Page 8 of 64
Test Conditions/Comments
Reg 17h[2:0] = 000. See Table 32 .
Reg 17h[2:0] = 001. See Table 32.
Reg 17h[2:0] = 010. See Table 32.
Reg 17h[2:0] = 100. See Table 32.
Reg 17h[2:0] = 101. See Table 32.
Reg 17h[2:0] = 110. See Table 32.
VCM = 2.0 V, VDIFF = 0 V
8 bits, 255 steps
Reg 15h[7:0]. See Table 30.
VCSCM = 2.0V, 0°C ≤ TA ≤ 85 OC SHRS =
SHRO = 2 V. Gain = 230x
Chopper ON
Chopper OFF
Input voltage range at CS+, CS−
34.0 mV – 44.5 mV. Gain = 65×
26.0 mV – 34.0 mV. Gain = 85×
20.0 mV – 26.0 mV. Gain = 110×
16.0 mV – 20.0 mV. Gain = 135×
12.0 mV – 16.0 mV. Gain = 175×
9.5 mV – 12.0 mV. Gain = 230×
VZO = 0
Reg 06h[7:1]. See Table 15.
SHRS = SHRO = 1 V
7 bits, 127 steps ISHARE slope
0 V ≤ VCSCM ≤ 0.3 V. Gain = 65×
VCSCM = Input Common Mode
VCSCM = 2.0V, 0°C ≤ TA ≤ 85°C
Gain = 135×
VCSCM = 2.0 V, 0°C ≤ TA ≤ 85°C
Gain = 65×
See Figure 13.
Reg 17h[7] = 1. See Table 32.
Reg 17h[5] = 1. See Table 32.
0 ≤ VTRIM ≤ 1.25 V
8 bits, 255 steps, VCT = 1.0 V
Reg 05h[7:0]. See Table 14.
Reg 17h[7] = 1. See Table 32.
Reg 06h = FEh. See Table 15.
Reg 17h[5] = 0, VSHARE = 2 V. Table 31
Reg 17h[5] = 1. See Table 32.
Reg 15h = 05h, approx 1 µA.
See Table 30. VSHARE = 2 V.
Gain setting = 4.5
Gain setting = 2.57
See Current Transformer Input
Section.
15 steps Reg 15h[3:0].
See Table 30.
See Figure 38. See Absolute
Maximum Ratings.
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