ADJD-S313-QR999 Просмотр технического описания (PDF) - Avago Technologies
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ADJD-S313-QR999 Datasheet PDF : 16 Pages
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The SCL clock line synchronizes the serial data
transmission on the SDA data line. It is always
generated by the master. The frequency of the SCL
clock line may vary throughout the transmission as
long as it still meets the minimum timing
requirements.
The master by default drives the SDA data line. The
slave drives the SDA data line only when sending
an acknowledge bit after the master writes data to
the slave or when the master requests the slave to
send data.
The SDA data line driven by the master may be
implemented on the negative edge of the SCL clock
line. The master may sample data driven by the
slave on the positive edge of the SCL clock line.
Figure shows an example of a master
implementation and how the SCL clock line and
SDA data line can be synchronized.
A complete data transfer is 8-bits long or 1-byte.
Each byte is sent most significant bit (MSB) first
followed by an acknowledge or not acknowledge
bit. Each data transfer can send an unlimited
number of bytes (depending on the data format).
SDA data sampled on the
positive edge of SCL
SDA
SCL
SDA data driven on the
negative edge of SCL
Figure 3. Data Bit Synchronization
Acknowledge/Not acknowledge
The receiver must always acknowledge each byte
sent in a data transfer. In the case of the slave-
receiver and master-transmitter, if the slave-
receiver does not send an acknowledge bit, the
master-transmitter can either STOP the transfer or
generate a repeated START to start a new transfer.
SDA
MSB
SCL S
or
Sr
1
2
START or repeated
START condition
Figure 4. Data Byte Transfer
SDA
(SLAVE-RECEIVER)
SDA
(MASTER-TRANSMITTER)
SCL
(MASTER)
Figure 5. Slave-Receiver Acknowledge
LSB ACK MSB
8
9
1
2
P
LSB
NO
ACK
Sr
8
9
Sr
or
P
STOP or repeated
START condition
SDA pulled LOW
by receiver
LSB
8
Acknowledge
SDA left HIGH
by transmitter
9
Acknowledge
clock pulse
9
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