ADJD-S312-CR999 Просмотр технического описания (PDF) - Avago Technologies
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ADJD-S312-CR999 Datasheet PDF : 18 Pages
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A complete data transfer is 8-bits long or 1-byte. Each
byte is sent most significant bit (MSB) first followed by an
acknowledge or not acknowledge bit. Each data transfer
can send an unlimited number of bytes (depending on
the data format). See Figure 4.
Acknowledge/Not acknowledge
The receiver must always acknowledge each byte sent
in a data transfer. In the case of the slave-receiver and
master-transmitter, if the slave-receiver does not send an
acknowledge bit, the master-transmitter can either STOP
the transfer or generate a repeated START to start a new
transfer. See Figure 5.
In the case of the master-receiver and slave-transmitter,
the master generates a not acknowledge to signal the
end of the data transfer to the slave-transmitter. The mas-
ter can then send a STOP or repeated START condition to
begin a new data transfer.
In all cases, the master generates the acknowledge or not
acknowledge SCL clock pulse. See Figure 6.
SDA
MSB
SCL
S
or
Sr
1
2
START or repeated
START condition
Figure 4: Data Byte Transfer
SDA
(SLAVE-RECEIVER)
LSB
ACK
MSB
8
9
1
2
P
LSB
NO
ACK
Sr
8
9
Sr
or
P
STOP or repeated
START condition
SDA pulled LOW
by receiver
Acknowledge
SDA
(MASTER-TRANSMITTER)
SCL
(MASTER)
Figure 5: Slave-Receiver Acknowledge
LSB
SDA left HIGH
by transmitter
8
9
Acknowledge
clock pulse
SDA
(SLAVE-TRANSMITTER)
SDA
(MASTER-RECEIVER)
SCL
(MASTER)
Figure 6: Master-Receiver Acknowledge
LSB
SDA left HIGH
by transmitter
SDA left HIGH
by receiver
8
Not
acknowledge
9
Acknowledge
clock pulse
P
Sr
STOP or repeated
START condition
10
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