ADIS16265 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADIS16265 Datasheet PDF : 20 Pages
| |||
Data Sheet
ADIS16260/ADIS16265
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tDATARATE
tSTALL
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Description
Serial clock
Data rate period
Stall period between data
Chip select to clock edge
Data output valid after SCLK falling
edge2
Data input setup time before SCLK
rising edge
Data input hold time after SCLK
rising edge
Data output fall time
Data output rise time
CS high after SCLK edge3
Normal Mode
Low Power Mode
(SMPL_PRD[7:0] ≤ 0x07, fS ≥ 64 Hz) (SMPL_PRD[7:0] ≥ 0x08, fS ≤ 56.9 Hz)
Min1
Typ
Max1
Min1
Typ
Max1
Unit
0.01
2.5
0.01
1.0
MHz
32
42
µs
9
12
µs
48.8
48.8
ns
100
100
ns
24.4
24.4
ns
48.8
48.8
ns
5
12.5
5
12.5
ns
5
12.5
5
12.5
ns
5
5
ns
1 Guaranteed by design; not production tested.
2 The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and
are governed by this specification.
3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state.
Timing Diagrams
CS
tDATARATE
SCLK
tSTALL
Figure 2. SPI Chip Select Timing
CS
SCLK
DOUT
DIN
tCS
1
* MSB
R/W
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
*NOT DEFINED
Figure 3. SPI Timing (Using SPI Settings Typically Identified as CPOL = 1, CPHA = 1)
Rev. D | Page 5 of 20
Share Link: 