ADIS16265 Просмотр технического описания (PDF) - Analog Devices
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ADIS16265 Datasheet PDF : 20 Pages
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ADIS16260/ADIS16265
BASIC OPERATION
The ADIS16260 and ADIS16265 require only power, ground,
and the four SPI signals to produce data and make it available
to an embedded processor. Figure 9 provides a schematic for
connecting the ADIS16260 and ADIS16265 to a SPI-compatible
processor and includes one of the configurable digital I/O lines.
The MSC_CTRL[2:0] bits are used to configure this line as a data
ready indicator (see the Data Ready I/O Indicator section).
INPUT/OUTPUT LINES ARE COMPATIBLE
WITH 3.3V OR 5V LOGIC LEVELS
5V
VDD
16
17
VCC VCC
SS
4 CS
SCLK
SYSTEM
PROCESSOR MOSI
SPI MASTER
MISO
1 SCLK
ADIS16260/
3 DIN ADIS16265
SPI SLAVE
2 DOUT
IRQ
5 DIO1
GND GND
18
19
Figure 9. Electrical Connection Diagram
Table 5. Generic Master Processor Pin Names and Functions
Pin Name
Function
SS
Slave select
IRQ
Interrupt request input
MOSI
Master output, slave input
MISO
Master input, slave output
SCLK
Serial clock
Data Sheet
The ADIS16260 and ADIS16265 SPI interface supports full-
duplex serial communication (simultaneous transmit and
receive) and uses the bit sequence shown in Figure 11. Processor
platforms typically support SPI communication with general-
purpose serial ports that require some configuration in their
control registers. Table 6 provides a list of the most common
settings that require attention to initialize the serial port of a
processor for communication with the ADIS16260 and
ADIS16265.
Table 6. Generic Master Processor SPI Settings
Processor Setting Description
Master
The ADIS16260 and ADIS16265 operate
as slaves
SCLK Rate ≤ 2.5 MHz Bit rate setting (SMPL_PRD[7:0] ≤ 0x07)
SPI Mode 3
Clock polarity, phase (CPOL = 1, CPHA = 1)
MSB First Mode
Bit sequence
16-Bit Mode
Shift register/data length
User registers govern all data collection and configuration.
Table 7 provides a memory map that includes all user registers,
along with references to the bit assignment tables that follow the
generic bit assignments in Figure 10.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UPPER BYTE
LOWER BYTE
Figure 10. Generic Register Bit Definitions
CS
SCLK
DIN
DOUT
R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
NOTES
1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
Figure 11. SPI Communication Bit Sequence
R/W A6 A5
DB15 DB14 DB13
Rev. D | Page 10 of 20
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