ADIS16240 Просмотр технического описания (PDF) - Analog Devices
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ADIS16240 Datasheet PDF : 20 Pages
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ADIS16240
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tDATARATE
tCS
tDAV
tDSU
tDHD
tDF
tDR
tSFS
Description
Serial clock rate2
Chip select period2
Chip select to clock edge
Data output valid after SCLK edge
Data input setup time before SCLK rising edge
Data input hold time after SCLK rising edge
Data output fall time
Data output rise time
CS high after SCLK edge
1 Guaranteed by design; typical specifications are not tested or guaranteed.
2 Based on sample rate selection.
Timing Diagrams
CS
SCLK
tDATARATE
Figure 2. SPI Chip Select Timing
Data Sheet
Min1
0.01
60
120
20
20
430
Typ
Max1
Unit
2.5
MHz
μs
ns
30
ns
ns
ns
10
25
ns
10
25
ns
ns
CS
SCLK
DOUT
DIN
tCS
1
MSB
W/R
2
3
4
5
6
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6
A5
A4
A3
A2
15
16
tSFS
DB2
DB1
LSB
D2
D1
LSB
Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. C | Page 4 of 20
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