ADIS16223 Просмотр технического описания (PDF) - Analog Devices

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ADIS16223

Digital Tri-Axial Vibration Sensor

Analog Devices 

ADIS16223

Data Sheet

BASIC OPERATION

The ADIS16223 uses a SPI for communication, which enables

Table 8 provides a list of user registers with their lower byte

a simple connection with a compatible, embedded processor

addresses. Each register consists of two bytes that each have its

platform, as shown in Figure 8. The factory default configuration

own, unique 6-bit address. Figure 9 relates each register’s bits to

for DIO1 provides a busy indicator signal that transitions low

their upper and lower addresses.

when a capture event completes and data is available for user

access. Use the DIO_CTRL register in Table 28 to reconfigure

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIO1 and DIO2, if necessary.

UPPER BYTE

LOWER BYTE

VDD

+3.3V

Figure 9. Generic Register Bit Definitions

SPI WRITE COMMANDS

8

SYSTEM

PROCESSOR

SPI MASTER

SS

SCLK

MOSI

MISO

IRQ1

E IRQ2

14 CS ADIS16223

SPI SLAVE

13 SCLK

11 DIN

12 DOUT

5 DIO1

3 DIO2

1 4 9 10

T Figure 8. Electrical Hook-Up Diagram

Table 6. Generic Master Processor Pin Names and Functions

E Pin Name

Function

SS

Slave select

IRQ1, IRQ2

Interrupt request inputs (optional)

L MOSI

Master output, slave input

MISO

Master input, slave output

SCLK

Serial clock

The ADIS16223 SPI interface supports full duplex serial

O communication (simultaneous transmit and receive) and uses

the bit sequence shown in Figure 12. Table 7 provides a list of

the most common settings that require attention to initialize a

processor’s serial port for the ADIS16223 SPI interface.

S Table 7. Generic Master Processor SPI Settings

Processor Setting Description

Master

ADIS16223 operates as a slave

B SCLK Rate ≤ 2.25 MHz Bit rate setting

SPI Mode 3

Clock polarity/phase (CPOL = 1, CPHA = 1)

MSB-First

Bit sequence

O 16-Bit

Shift register/data length

User control registers govern many internal operations. The

DIN bit sequence in Figure 12 provides the ability to write to

these registers, one byte at a time. Some configuration changes

and functions only require one write cycle. For example, set

GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture

sequence. The manual capture starts immediately after the last bit

clocks into DIN (16th SCLK rising edge). Other configurations may

require writing to both bytes.

CS

SCLK

DIN

Figure 10. SPI Sequence for Manual Capture Start (DIN = 0xBF08)

SPI READ COMMANDS

A single register read requires two 16-bit SPI cycles that also use

the bit assignments in Figure 12. The first sequence sets R/W = 0

and communicates the target address (Bits[A6:A0]). Bits[D7:D0]

are don’t care bits for a read DIN sequence. DOUT clocks out the

requested register contents during the second sequence. The

second sequence can also use DIN to setup the next read. Figure 11

provides a signal diagram for all four SPI signals while reading

the x-axis acceleration capture buffer (CAPT_BUFFX) in a

repeating pattern. In this diagram, DIN = 0x1400 and DOUT

reflects the CAPT_BUFFX register contents from the previous

DIN read-request sequence.

CS

SCLK

DIN

DIN = 0001 0100 0000 0000 = 0x1400

DOUT

DOUT = 1111 1001 1101 1010 = 0xF9DA = –1574 LSBs = ~7.505 g

Figure 11. Example SPI Read, Second 16-Bit Sequence

CS

SCLK

DIN

DOUT

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

NOTES

1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).

Figure 12. Example SPI Read Sequence

R/W A6 A5

DB15 DB14 DB13

Rev. A | Page 8 of 20

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