ADF7012 Просмотр технического описания (PDF) - Analog Devices
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ADF7012 Datasheet PDF : 28 Pages
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ADF7012
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD 1
24 CREG2
CREG1 2
23 RSET
CPOUT 3
TxDATA 4
TSSOP
22 AGND
21 DVDD
TxCLK 5 ADF7012 20 RFOUT
MUXOUT 6 TOP VIEW 19 RFGND
DGND 7 (Not to Scale) 18 VCOIN
OSC1 8
17 CVCO
OSC2 9
16 L2
CLKOUT 10
CLK 11
15 L1
14 CE
DATA 12
13 LE
Figure 3. Pin Configuration
Table 4. Pin Functional Descriptions
Pin No. Mnemonic Description
1
DVDD
Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin.
2
CREG1
A 1 μF capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor improves
regulator power-on time, but may cause higher spurious noise.
3
CPOUT
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current
changes the control voltage on the input to the VCO.
4
TxDATA
Digital data to be transmitted is input on this pin.
5
TxCLK
GFSK and GOOK Only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7012. The
clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on the falling edge of TxCLK.
The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
6
MUXOUT Provides the Lock_Detect Signal. This signal is used to determine if the PLL is locked to the correct frequency. It also
provides other signals, such as Regulator_Ready, which is an indicator of the status of the serial interface regulator, and a
voltage monitor (see the MUXOUT Modes section for more information).
7
DGND
Ground for Digital Section.
8
OSC1
The reference crystal should be connected between this pin and OSC2.
9
OSC2
The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving this pin
with CMOS levels, and powering down the crystal oscillator bit in software.
10
CLKOUT
A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive several
other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
11
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance
CMOS input.
13
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches,
the latch being selected using the control bits.
14
CE
Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1μA. Register values are lost when
CE is low and the part must be reprogrammed once CE is brought high.
15
L1
Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the value of the
inductor to be connected between L1 and L2.
16
L2
Connected to external printed or discrete inductor.
17
CVCO
A 22 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012. This
capacitor is necessary to ensure stable VCO operation.
18
VCOIN
The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the
tuning voltage, the higher the output frequency.
19
RFGND
20
RFOUT
Ground for Output Stage of Transmitter.
The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output should be
impedance matched using suitable components to the desired load. See the PA Matching section.
21
DVDD
Voltage supply for VCO and PA section. This should have the same supply as DVDD (Pin 1), and should be between 2.3 V and
3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
22
AGND
Ground Pin for the RF Analog Circuitry.
23
RSET
24
CREG2
External Resistor to set charge pump current and some internal bias currents. Use 3.6 kΩ as default.
Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator
power-on time and phase noise, but may have stability issues over the supply and temperature.
Rev. A | Page 7 of 28
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