ADF7011 Просмотр технического описания (PDF) - Analog Devices
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ADF7011 Datasheet PDF : 24 Pages
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RF N Register
ADF7011
8-BIT INTEGER-N
12-BIT FRACTIONAL-N
CONTROL
BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LDP V1 N8 N7 N6 N5 N4 N3 N2 N1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C2 (0) C1 (1)
e.g., SETTING F = 0 IN FSK MODE TURNS ON THE
⌺-⌬ WHILE THE PLL IS AN INTEGER VALUE
M12
M11
M10
..........
M3
M2
M1
MODULUS
DIVIDE RATIO
0
0
0
0
0
0
.
.
.
.
.
.
1
1
0
..........
1
0
..........
1
0
..........
1
.
..........
.
.
..........
.
.
..........
.
1
..........
1
0
0
0
1
1
0
.
.
.
.
.
.
0
0
4
5
6
.
.
.
4092
1
1
1
..........
1
0
1
4093
1
1
1
..........
1
1
0
4094
1
1
1
..........
1
1
1
4095
e.g., MODULUS DIVIDE RATIO = 2048 –> FRACTION 1/2
N8
N7
N6
N5
N4
N3
N2
N1
N COUNTER
DIVIDE RATIO
0
0
0
1
1
1
1
1
31
0
0
1
0
0
0
0
0
32
0
0
1
0
0
0
0
1
33
0
0
1
0
0
0
1
0
34
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
0
1
253
1
1
1
1
1
1
1
0
254
1
1
1
1
1
1
1
1
255
V1
VCO BAND
(MHz)
0
866–870
1
433–435
LDP
0
1
LOCK DETECT
PRECISION
3 CYCLES < 15ns
5 CYCLES < 15ns
THE N VALUE CHOSEN IS A MINIMUM OF
P2 + 3P + 3. FOR PRESCALER = 8/9, THIS
MEANS A MINIMUM N DIVIDE OF 91.
REV. 0
–11–
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