ADF4113HVBRUZ(Rev0) Просмотр технического описания (PDF) - Analog Devices
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ADF4113HVBRUZ Datasheet PDF : 20 Pages
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ADF4113HV
SPECIFICATIONS
AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; RSET = 4.7 kΩ; dBm referred to 50 Ω;
TA = TMIN to TMAX, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.
Table 1.
Parameter
B Version
B Chips1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Sensitivity
−15/0
−15/0
dBm min/max
RF Input Frequency
0.2/3.7
0.2/3.7
GHz min/max For lower frequencies, ensure SR > 130 V/μs
Prescaler Output Frequency2
165
165
MHz max
RF CHARACTERISTICS (5 V)
RF Input Sensitivity
−10/0
−10/0
dBm min/max
RF Input Frequency
0.2/3.7
0.2/3.7
GHz min/max For lower frequencies, ensure SR > 130 V/μs
0.2/4.0
0.2/4.0
GHz min/max Input level = −5 dBm
Prescaler Output Frequency
200
200
MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency
Reference Input Sensitivity
5/150
0.4/AVDD
1.0/AVDD
5/150
0.4/AVDD
1.0/AVDD
MHz min/max
V p-p min/max
V p-p min/max
For f < 5 MHz, ensure SR > 100 V/μs
AVDD = 3.3 V, biased at AVDD/23
For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/23, 4
REFIN Input Capacitance
10
10
pF max
REFIN Input Current
±100
±100
μA max
PHASE DETECTOR FREQUENCY
5
5
MHz max
CHARGE PUMP
ICP Sink/Source
RSET = 4.7 kΩ
High Value
640
640
μA typ
Low Value
80
80
μA typ
Absolute Accuracy
2.5
2.5
% typ
RSET Range
3.9/10
3.9/10
kΩ typ
ICP Three-State Leakage Current
5
5
nA max
Sink and Source Current Matching 3
3
% typ
1 V ≤ VCP ≤ VP – 1 V
ICP vs. VCP
1.5
1.5
% typ
1 V ≤ VCP ≤ VP – 1 V
ICP vs. Temperature
2
2
% typ
VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage
0.8 × DVDD
0.8 × DVDD V min
VINL, Input Low Voltage
0.2 × DVDD
0.2 × DVDD V max
IINH/IINL, Input Current
±1
±1
μA max
CIN, Input Capacitance
10
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
DVDD − 0.4
DVDD − 0.4 V min
IOH = 500 μA
VOL, Output Low Voltage
0.4
0.4
V max
IOL = 500 μA
POWER SUPPLIES
AVDD
2.7/5.5
2.7/5.5
V min/V max
DVDD
AVDD
AVDD
VP
IDD5 (AIDD + DIDD)
13.5/16.5
16
13.5/16.5
11
V min/V max
mA max
11 mA typical
IP
0.25
0.25
mA max
TA = 25°C
Low Power Sleep Mode
1
1
μA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor6
−212
−212
dBc/Hz typ
1 The B chip specifications are given as typical values.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AC coupling ensures AVDD/2 bias.
4 Guaranteed by characterization.
5 TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.
6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logfPFD: PNSYNTH = PNTOT − 10logfPFD − 20logN.
Rev. 0 | Page 3 of 20
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