AD9991KCPRL Просмотр технического описания (PDF) - Analog Devices

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AD9991KCPRL

10-Bit CCD Signal Processor with Precision Timing ™ Generator

Analog Devices 

AD9991

SYSTEM OVERVIEW

Figure 1 shows the typical system block diagram for the AD9991

used in Master mode. The CCD output is processed by the

AD9991’s AFE circuitry, which consists of a CDS, VGA, black

level clamp, and A/D converter. The digitized pixel information

is sent to the digital image processor chip, which performs the

postprocessing and compression. To operate the CCD, all CCD

timing parameters are programmed into the AD9991 from the

system microprocessor through the 3-wire serial interface. From

the system master clock, CLI, provided by the image processor

or external crystal, the AD9991 generates all of the CCD’s hori-

zontal and vertical clocks and all internal AFE clocks. External

synchronization is provided by a SYNC pulse from the micropro-

cessor, which will reset internal counters and resync the VD and

HD outputs.

Alternatively, the AD9991 may be operated in Slave mode, in

which VD and HD are provided externally from the image pro-

cessor. In this mode, all AD9991 timing will be synchronized

with VD and HD.

V-DRIVER

V1–V6, VSG1–VSG5, SUBCK

CCD

H1–H4, RG, VSUB

CCDIN

MSHUT

STROBE

AD9991

AFETG

DOUT

DCLK

HD, VD

CLI

SYNC

SERIAL

INTERFACE

DIGITAL

IMAGE

PROCESSING

ASIC

The H-drivers for H1–H4 and RG are included in the AD9991,

allowing these clocks to be directly connected to the CCD.

H-drive voltage of up to 3.3 V is supported. An external V-driver

is required for the vertical transfer clocks, the sensor gate pulses,

and the substrate clock.

The AD9991 also includes programmable MSHUT and

STROBE outputs, which may be used to trigger mechanical

shutter and strobe (flash) circuitry.

Figures 2 and 3 show the maximum horizontal and vertical

counter dimensions for the AD9991. All internal horizontal and

vertical clocking is controlled by these counters to specify line

and pixel locations. Maximum HD length is 4095 pixels per line,

and maximum VD length is 4095 lines per field.

MAXIMUM

FIELD

DIMENSIONS

12-BIT HORIZONTAL = 4096 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

Figure 1. Typical System Block Diagram, Master Mode

Figure 2. Vertical and Horizontal Counters

MAX VD LENGTH IS 4095 LINES

VD

MAX HD LENGTH IS 4095 PIXELS

HD

CLI

Figure 3. Maximum VD/HD Dimensions

REV. 0

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