AD9923A Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

AD9923A

Parameter

SCK Falling Edge to SDATA Valid Hold

SCK Falling Edge to SDATA Valid Read

INHIBIT REGION FOR SHP AND SHD WITH

RESPECT TO H-CLOCK EDGE LOCATION

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 0

Conditions/Comments

Symbol

tDH

tDV

tSHDINH

HxMASK = 0, HxRETIME = 0, HxPOLARITY = 1

tSHDINH

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 0

tSHPINH

HxMASK = 0, HxRETIME = 1, HxPOLARITY = 1

tSHPINH

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 0

tSHDINH

HxMASK = 1, HxRETIME = 0, HxPOLARITY = 1

tSHDINH

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 0

tSHPINH

HxMASK = 1, HxRETIME = 1, HxPOLARITY = 1

tSHPINH

Min

Typ Max

10

10

HxPOS − 9

HxNEG − 9

HxPOS − 7

HxNEG − 7

HxNEG − 9

HxPOS − 9

HxNEG − 7

HxPOS − 7

HxPOS − 18

HxNEG − 18

HxPOS − 16

HxNEG − 16

HxNEG − 18

HxPOS − 18

HxNEG − 16

HxPOS − 16

1 Parameter is programmable.

2 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

Unit

ns

ns

Edge

location

Edge

location

Edge

location

Edge

location

Edge

location

Edge

location

Edge

location

Edge

location

Rev. A | Page 7 of 84

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