AD9923A Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание

производитель

AD9923A

CCD Signal Processor with V-Driver and Precision Timing Generator

Analog Devices 

Parameter

VMM to VH

VH to VMM

VMM to VLL

Rise Time

VLL to VH

VLL to VMM

VMM to VH

Fall Time

VH to VLL

VH to VMM

VMM to VLL

Output Currents

at −7.25 V

at −0.25 V

at +0.25 V

at +14.75 V

RON

Conditions/Comments

AD9923A

Symbol

tPMH

tPHM

tPML

tRLH

tRLM

tRMH

tFHL

tFHM

tFML

Min Typ Max Unit

25

ns

30

ns

25

ns

40

ns

45

ns

30

ns

40

ns

90

ns

25

ns

20

mA

12

mA

12

mA

20

mA

35

Ω

V-DRIVER

INPUT

50%

50%

V-DRIVER

OUTPUT

tRLM, tRMH, tRLH

90%

tPLM, tPMH, tPLH

10%

tPML, tPHM, tPHL

90%

tFML, tFHM, tFHL

10%

Figure 2. Definition of V-Driver Timing Specifications

ANALOG SPECIFICATIONS

AVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter

CDS

Allowable CCD Reset Transient

CDS Gain Accuracy

−3 dB CDS Gain

0 dB CDS Gain

+3 dB CDS Gain

+6 dB CDS Gain

Maximum Input Range Before Saturation

0 dB CDS Gain

−3 dB CDS Gain

+6 dB CDS Gain

Maximum CCD Black Pixel Amplitude

0 dB CDS Gain (Default)

+6 dB CDS Gain

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution

Gain Monotonicity

Gain Range

Minimum Gain (VGA Code 15)

Maximum Gain (VGA Code 1023)

Conditions/Comments

Input characteristics definition1

VGA gain = 6 dB (Code 15, default value)

Default

Default setting

Positive offset definition1

Min Typ

0.5

−3 −2.5

0

+0.5

+3 +3.5

+5.5 +6

1.0

1.4

0.5

−100

−50

1024

Guaranteed

6

42

Max Unit

1.2 V

−2 dB

+1 dB

+4 dB

+6.5 dB

V p-p

V p-p

V p-p

+200 mV

+100 mV

Steps

dB

dB

Rev. A | Page 5 of 84

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