AD9888 Просмотр технического описания (PDF) - Analog Devices
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AD9888 Datasheet PDF : 36 Pages
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Data Sheet
AD9888
Table 4. Pin Function Descriptions
Mnemonic Description
Inputs
RAIN0
Channel 0 Analog Input for Red.
GAIN0
Channel 0 Analog Input for Green.
BAIN0
Channel 0 Analog Input for Blue.
RAIN1
Channel 1 Analog Input for Red.
GAIN1
Channel 1 Analog Input for Green.
BAIN1
Channel 1 Analog Input for Blue.
These high impedance inputs accept red, green, and blue channel graphics signals, respectively. The six channels are
identical and can be used for any color; colors are assigned for convenient reference. They accommodate input signals
ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation.
HSYNC0
Channel 0 Horizontal Sync Input.
HSYNC1
Channel 1 Horizontal Sync Input.
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference
for pixel clock generation. The logic sense of this pin is controlled by the HSYNC input polarity control (Register 0x0E, Bit 6).
Only the leading edge of HSYNC is used by the PLL. The trailing edge is used for clamp timing only. When the HSYNC input
polarity control = 0, the falling edge of HSYNC is used. When the HSYNC polarity control = 1, the rising edge is active. The
input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.
VSYNC0
Channel 0 Vertical Sync Input.
VSYNC1
Channel 1 Vertical Sync Input.
These are the inputs for vertical sync.
SOGIN0
Channel 0 Sync-on-Green Input.
SOGIN1
Channel 1 Sync-on-Green Input.
These inputs are provided to assist in processing signals with embedded sync, typically on the green channel. These pins
are connected to a high speed comparator with an internally generated, variable threshold level, which is nominally set to
0.15 V above the negative peak of the input signal. When connected to an ac-coupled graphics signal with embedded
sync, these pins produce a noninverting digital output on SOGOUT. This output is usually a composite sync signal,
containing both vertical and horizontal sync information. When not used, these inputs should be left unconnected. For
more details about this function and how it should be configured, see the Sync-on-Green Input section.
CLAMP
External Clamp Input.
This logic input can be used to define the time during which the input signal is clamped to the reference dc level (to
ground for RGB or to midscale for YUV). It should be used when the reference dc level is known to be present on the
analog input channels, typically during a period following HSYNC, called the back porch, when a good black reference is
provided. The CLAMP pin is enabled by setting the external clamp control (Register 0x0F, Bit 7) to 1 (default is 0). When
disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the
trailing edge of the HSYNC input. The logic sense of this pin is controlled by the clamp polarity control (Register 0x0F, Bit 6).
When not used, this pin should be grounded and the external clamp should be programmed to 0.
COAST
Clock Generator Coast Input (optional).
This input can be used to stop the pixel clock generator from synchronizing with HSYNC while continuing to produce a
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal
sync pulses during the vertical interval or that include equalization pulses. The COAST signal is usually not required for PC
generated signals. The logic sense of this pin is controlled by the coast polarity control (Register 0x0F, Bit 3). When this pin
is not used, either ground the pin and program the coast polarity to 1 or tie the pin high (to VD through a 10 kΩ resistor)
and program the coast polarity to 0. The coast polarity register bit defaults to 1 at power-up.
CKEXT
External Clock Input (optional).
This pin can be used to provide an external clock to the AD9888 in place of the clock internally generated from HSYNC. The
external clock is enabled by programming the external clock select bit (Register 0x15, Bit 0) to 1. When an external clock is
used, all other internal functions operate normally. When not used, this pin should be tied through a 10 kΩ resistor to
ground, and the external clock register should be programmed to 0. The clock phase adjustment still operates when an
external clock source is used.
CKINV
Sampling Clock Inversion (optional).
This pin can be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This
supports the alternate pixel sampling mode, wherein higher frequency input signals (up to 410 MSPS) can be captured by
first sampling the odd pixels, and then capturing the even pixels on the subsequent frame. This pin should be used only
during blanking intervals (typically vertical blanking) because it might produce several samples of corrupted data during
the phase shift. When not in use, this pin should be grounded.
Rev. C | Page 9 of 36
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