AD9888 Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD9888 Datasheet PDF : 36 Pages
| |||
Data Sheet
AD9888
Parameter
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle
DATACK, DATACK
Output Coding
POWER SUPPLY
Analog Power Supply Voltage (VD)
Output Power Supply Voltage (VDD)
PLL Power Supply Voltage (PVD)
Analog Power Supply Current (ID)
Output Power Supply Current (IDD)4
PLL Power Supply Current (IPVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power5
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)6
Without Harmonics, fIN = 40.7 MHz
Crosstalk
THERMAL CHARACTERISTICS
Junction-to-Case Thermal
Resistance (θJC)
Junction-to-Ambient Thermal
Resistance (θJA)
Temp
Full
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
25°C
Full
Full
AD9888KSZ-100/-1401
Test
Level Min
Typ
Max
VI
2.5
VI
0.8
IV
−1.0
IV
+1.0
V
3
VI
VD − 0.1
VI
0.1
IV
44
IV
49
55
Binary
IV
3.0
3.3
IV
2.2
3.3
IV
3.0
3.3
200
50
8
VI
850
VI
12
VI
40
3.6
3.6
3.6
1050
20
66
V
500
V
2
V
1.5
IV
42
45
V
44
V
50
V
8.4
V
35
AD9888KSZ-170
Min
Typ
Max
2.5
0.8
−1.0
+1.0
3
VD − 0.1
44
49
55
Binary
3.0
3.3
2.2
3.3
3.0
3.3
215
55
9
920
12
40
3.6
3.6
3.6
1150
20
66
500
2
1.5
41
44
43
50
8.4
35
Unit
V
V
μA
μA
pF
V
V
%
V
V
V
mA
mA
mA
mW
mA
mW
MHz
ns
ns
dB
dB
dBc
°C/W
°C/W
1 AD9888JS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.
2 See Figure 2.
3 The maximum specifications for the AD9888KS-100 and AD9888KS-140 were obtained with VCO range = 10, charge pump current = 100, PLL divider = 1693. The
maximum specifications for the AD9888KS-170 were obtained with VCO range = 11, charge pump current = 100, PLL divider = 2159.
4 DEMUX = 1, DATACK and DATACK load = 15 pF, data load = 5 pF.
5 Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, or 75 MHz.
6 Using an external pixel clock.
SDA
tBUFF
SCL
tSTAH
tDHO
tDAL
tDSU
tSTASU
tDAH
Figure 2. Serial Port Read/Write Timing
Rev. C | Page 5 of 36
tSTOSU
Share Link: 