AD9882 Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD9882

Dual Interface for Flat Panel Displays

Analog Devices 

RED

GREEN

BLUE

Data Output, RED Channel

VDD

Data Output, GREEN Channel

Data Output, BLUE Channel

These are the main data outputs. Bit 7 is the MSB.

The delay from pixel sampling time to output is

fixed. When the sampling time is changed by

adjusting the PHASE register, the output timing

is shifted as well. The DATACK and HSOUT

outputs are also moved, so the timing relation-

ship among the signals is maintained.

Please refer to the timing diagrams for more

information.

PVD

POWER SUPPLY

VD

Main Power Supply

These pins supply power to the main elements of

the circuit. They should be as quiet as possible.

GND

AD9882

Digital Output Power Supply

A large number of output pins (up to 25) switch-

ing at high speed (up to 140 MHz) generates a

lot of power supply transients. These supply

pins are identified separately from the VD pins

so special care can be taken to minimize out-

put noise transferred into the sensitive analog

circuitry.

If the AD9882 is interfacing with lower voltage

logic, VDD may be connected to a lower supply

voltage (as low as 2.2 V) for compatibility.

Clock Generator Power Supply

The most sensitive portion of the AD9882 is the

clock generation circuitry. These pins provide

power to the clock PLL and help the user design

for optimal performance. The designer should

provide noise-free power to these pins.

Ground

The ground return for all circuitry on chip. It is

recommended that the AD9882 be assembled on

a single solid ground plane, with careful attention

to ground current paths.

AIO

(0FH Bit 2)

1

0

Analog

Interface

Detect

X

0

0

1

1

Digital

Interface

Detect

X

0

1

0

1

Table III. Interface Selection Controls

AIS

(0FH Bit 1)

0

1

X

X

X

0

1

Active

Interface

Analog

Digital

None

Digital

Analog

Analog

Digital

Description

Force the analog interface active.

Force the digital interface active.

Neither interface was detected. Both interfaces are

powered down.

The digital interface was detected. Power down the

analog interface.

The analog interface was detected. Power down the

digital interface.

Both interfaces were detected. The analog interface

gets priority.

Both interfaces were detected. The digital interface

gets priority.

REV. A

–11–

Share Link: