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AD9877ABS Просмотр технического описания (PDF) - Analog Devices

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AD9877ABS Datasheet PDF : 37 Pages
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AD9877
Parameter
TIMING CHARACTERISTICS (10 pF Load)
Wake-Up Time
Minimum RESET Pulse Width Low (tRL)
Digital Output Rise/Fall Time
Tx/Rx Interface
MCLK Frequency (fMCLK)
TxSYNC/TxIQ Setup Time (tSU)
TxSYNC/TxIQ Hold Time (tHD)
MCLK Rising Edge to RxSYNC/RxIQ/IF Valid Delay (tMD)
REFCLK Rising or Falling Edge to RxSYNC/RxIQ/IF Valid
Delay (tOD)
REFCLK Edge to MCLK Falling Edge (tEE)
Serial Control Bus
Maximum SCLK Frequency (fSCLK)
Minimum Clock Pulse Width High (tPWH)
Minimum Clock Pulse Width Low (tPWL)
Maximum Clock Rise/Fall
Minimum Data/Chip-Select Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY
Supply Current, IS (Full Operation)
Analog Supply Current, IAS
Digital Supply Current, IDS
Supply Current, IS
Standby (PWRDN Pin Active)
Full Power-Down (Register 0x02 = 0xF9)
Power-Down Tx Path (Register 0x02 = 0x20)
Power-Down Rx Path (Register 0x02 = 0x19)
Reset (RESET Pin Active)
Power Supply Rejection (Differential Signal)
Tx DAC
8-Bit ADC
12-Bit ADC
Test
Temp Level
N/A N/A
N/A N/A
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
Full II
25°C II
25°C II
25°C II
25°C II
25°C III
25°C II
25°C II
25°C II
25°C III
25°C III
25°C I
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
25°C III
Min
Typ
Max
Unit
200
tMCLK cycles
5
tMCLK cycles
2.8
4
ns
3
3
0
TOSC/4 − 2.0
−1.0
66
MHz
ns
ns
1.0
ns
TOSC/4 + 3.0 ns
+1.0
ns
15
MHz
30
ns
30
ns
1
μs
25
ns
0
ns
30
ns
DRVDD − 0.7
V
0.4
V
12
μA
12
μA
3
pF
DRVDD − 0.6
V
0.4
V
233
272
mA
85
mA
228
mA
104
113
mA
10
mA
60
mA
265
mA
85
mA
<0.25
<0.004
<0.0004
% FS
% FS
% FS
Rev. B | Page 6 of 36

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