AD9874 Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9874

IF Digitizing Subsystem

Analog Devices 

AD9874–SPECIFICATIONS (VDDI = VDDF = VDDA = VDDC = VDDL = VDDD = VDDH = 2.7 V to 3.6 V,

VDDQ = VDDP = 2.7 V to 5.5 V, fCLK = 18 MSPS, fIF = 109.65 MHz, fLO = 107.4 MHz, fREF = 16.8 MHz, unless otherwise noted.)1

Parameter

SYSTEM DYNAMIC PERFORMANCE2

SSB Noise Figure @ Min VGA Attenuation3, 4

@ Max VGA Attenuation3, 4

Dynamic Range with AGC Enabled3, 4

IF Input Clip Point @ Max VGA Attenuation3

@ Min VGA Attenuation3

Input Third Order Intercept (IIP3)

Gain Variation over Temperature

Temp

Full

Full

Full

Full

Full

Full

Full

Test Level Min

Typ

Max

IV

8.1

9.5

IV

13

IV

91

95

IV

–20

–19

IV

–32

–31

IV

–5

0

IV

0.7

2

Unit

dB

dB

dB

dBm

dBm

dBm

dB

LNA + MIXER

Maximum RF and LO Frequency Range

LNA Input Impedance

Mixer LO Input Resistance

Full

25oC

25oC

IV

300

500

V

370//1.4

V

1

MHz

⍀//pF

k⍀

LO SYNTHESIZER

LO Input Frequency

Full

LO Input Amplitude

Full

FREF Frequency (for Sinusoidal Input ONLY)

Full

FREF Input Amplitude

Full

FREF Slew Rate

Full

Minimum Charge Pump Current @ 5 V5

Full

Maximum Charge Pump Current @ 5 V5

Full

Charge Pump Output Compliance6

Full

Synthesizer Resolution

Full

IV

7.75

300

MHz

IV

0.3

2.0

V p-p

IV

8

25

MHz

IV

0.3

3

V p-p

IV

7.5

V/␮s

VI

0.48

0.67

0.78

mA

VI

3.87

5.3

6.2

mA

VI

0.4

VDDP – 0.4 V

IV

6.25

kHz

CLOCK SYNTHESIZER

CLK Input Frequency

Full

CLK Input Amplitude

Full

Minimum Charge Pump Output Current5

Full

Maximum Charge Pump Output Current5

Full

Charge Pump Output Compliance6

Full

Synthesizer Resolution

Full

IV

13

26

MHz

IV

0.3

VDDC

V p-p

VI

0.48

0.67

0.78

mA

VI

3.87

5.3

6.2

mA

VI

0.4

VDDQ – 0.4 V

IV

2.2

kHz

SIGMA-DELTA ADC

Resolution

Clock Frequency (fCLK)

Center Frequency

Pass-Band Gain Variation

Alias Attenuation

Full

IV

16

24

Bits

Full

IV

13

26

MHz

Full

V

Full

IV

fCLK/8

1.0

MHz

dB

Full

IV

80

dB

GAIN CONTROL

Programmable Gain Step

AGC Gain Range (Continuous)

GCP Output Resistance

Full

V

16

dB

Full

V

12

dB

Full

IV

50

72.5

95

k⍀

OVERALL

Analog Supply Voltage

(VDDA, VDDF, VDDI)

Digital Supply Voltage

(VDDD, VDDC, VDDL)

Interface Supply Voltage7

(VDDH)

Charge Pump Supply Voltage

(VDDP, VDDQ)

Total Current

High Performance Setting8

Low Power Mode8

Standby

Full

VI

2.7

3.0

3.6

V

Full

VI

2.7

3.0

3.6

V

Full

VI

1.8

3.6

V

Full

VI

2.7

5.0

5.5

V

Full

VI

Full

VI

Full

VI

20

26.5

mA

17

22

mA

0.01

0.1

mA

OPERATING TEMPERATURE RANGE

–40

+85

°C

NOTES

1Standard operating mode: LNA/Mixer @ high bias setting, VGA @ Min ATTEN setting, synthesizers in normal (not fast acquire) mode, fCLK = 18 MHz, decimation

factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.

2This includes 0.9 dB loss of matching network.

3AGC with DVGA enabled.

4Measured in 10 kHz bandwidth.

5Programmable in 0.67 mA steps.

6Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).

7VDDH must be less than VDDD + 0.5 V.

8 Clock VCO off, add additional 0.7 mA with VGA @ Max ATTEN setting.

Specifications subject to change without notice.

REV. A

–3–

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