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AD9848(RevA) Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание
производитель
AD9848 Datasheet PDF : 32 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
AD9848/AD9849
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0 1
D1 2
D2 3
D3 4
D4 5
DVSS3 6
DVDD3 7
D5 8
D6 9
D7 10
D8 11
(MSB) D9 12
PIN 1
IDENTIFIER
AD9848
TOP VIEW
(Not to Scale)
36 SL
35 REFT
34 REFB
33 CMLEVEL
32 AVSS3
31 AVDD3
30 BYP3
29 CCDIN
28 BYP2
27 BYP1
26 AVDD2
25 AVSS2
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37
D2 1
D3 2
D4 3
D5 4
D6 5
DVSS3 6
DVDD3 7
D7 8
D8 9
D9 10
D10 11
(MSB) D11 12
PIN 1
IDENTIFIER
AD9849
TOP VIEW
(Not to Scale)
36 SL
35 REFT
34 REFB
33 CMLEVEL
32 AVSS3
31 AVDD3
30 BYP3
29 CCDIN
28 BYP2
27 BYP1
26 AVDD2
25 AVSS2
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Type* Description
1–5
1–5
6
7
8–12
8–12
13, 14
15
16
17, 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47, 48
47, 48
D0–D4
DO
D2–D6
DO
DVSS3
P
DVDD3
P
D5–D9
DO
D7–D11
DO
H1, H2
DO
DVSS1
P
DVDD1
P
H3, H4
DO
DVSS2
P
RG
DO
DVDD2
P
AVSS1
P
CLI
DI
AVDD1
P
AVSS2
P
AVDD2
P
BYP1
AO
BYP2
AO
CCDIN
AI
BYP3
AO
AVDD3
P
AVSS3
P
CMLEVEL
AO
REFB
AO
REFT
AO
SL
DI
SDI
DI
SCK
DI
CLPOB
DI
CLPDM
DI
HBLK
DI
PBLK
DI
VD
DI
HD
DI
DVSS4
P
DVDD4
P
NC
NC
D0, D1
DO
Data Outputs AD9848 Only
Data Outputs AD9849 Only
Digital Ground 3 – Data Outputs
Digital Supply 3 – Data Outputs
Data Outputs (D9 is MSB) AD9848 Only
Data Outputs (D9 is MSB) AD9849 Only
Horizontal Clocks (to CCD)
Digital Ground 1 – H Drivers
Digital Supply 1 – H Drivers
Horizontal Clocks (to CCD)
Digital Ground 1 – RG Driver
Reset Gate Clock (to CCD)
Digital Supply 2 – RG Driver
Analog Ground 1
Master Clock Input
Analog Supply 1
Analog Ground 2
Analog Supply 2
Bypass Pin (0.1 µF to AVSS)
Bypass Pin (0.1 µF to AVSS)
Analog Input for CCD Signal
Bypass Pin (0.1 µF to AVSS)
Analog Supply 3
Analog Ground 3
Internal Bias Level Decoupling (0.1 µF to AVSS)
Reference Bottom Decoupling (1.0 µF to AVSS)
Reference Top Decoupling (1.0 µF to AVSS)
3-Wire Serial Load (from µP)
3-Wire Serial Data Input (from µP)
3-Wire Serial Clock (from µP)
Optical Black Clamp Pulse
Dummy Black Clamp Pulse
HCLK Blanking Pulse
Preblanking Pulse
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA
Digital Supply 4 – VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL, SDATA
Internally Not Connected AD9848 Only
Data Output (D0 is LSB) AD9849 Only
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
–8–
REV. A

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