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AD9755AST(Rev0) Просмотр технического описания (PDF) - Analog Devices

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производитель
AD9755AST
(Rev.:Rev0)
ADI
Analog Devices ADI
AD9755AST Datasheet PDF : 26 Pages
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AD9753
0.1F
RSET
2k
3.1V TO 3.5V
1.2V REF
REFIO
DVDD AVDD
PMOS CURRENT
SOURCE ARRAY
FSADJ
SEGMENTED
SWITCHES FOR
DB0 TO DB11
DAC
DAC LATCH
AD9753
DCOM
ACOM
2 -1 MUX
PORT 1 LATCH
PORT 2 LATCH
DB0 DB11
DB0 DB11
DIGITAL DATA INPUTS
PLL
CIRCUITRY
VDIFF = VOUTA VOUTB
IOUTA
IOUTB
PLLVDD
CLKVDD
CLK+
CLK
CLKCOM
RESET
LPF
VOUT B
RLOAD
50
VOUT A
RLOAD
50
DIV0 DIV1 PLLLOCK
Figure 3. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9753. The
AD9753 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, IOUTFS. The array is
divided into 31 equal sources that make up the five most signifi-
cant bits (MSBs). The next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an MSB cur-
rent source. The remaining LSBs are a binary weighted fraction
of the middle bit current sources. Implementing the middle
and lower bits with current sources, instead of an R-2R ladder,
enhances dynamic performance for multitone or low-amplitude
signals and helps maintain the DAC’s high output impedance
(i.e., >100 k).
All of the current sources are switched to one or the other of the
two outputs (i.e., IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on a new architecture that
drastically improves distortion performance. This new switch
architecture reduces various timing errors and provides match-
ing complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9753 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.1 V to 3.5 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V bandgap voltage refer-
ence and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET. The external resistor, in combination
with both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 times the value of IREF.
REFERENCE OPERATION
The AD9753 contains an internal 1.20 V bandgap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1 µF capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier with
an input bias current less than 100 nA should be used. An example
of the use of the internal reference is given in Figure 4.
A low impedance external reference can be applied to REFIO as
shown in Figure 5. The external reference may provide either a
fixed reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. Note that the
0.1 µF compensation capacitor is not required since the internal
reference is overdriven, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
ADDITIONAL
EXTERNAL
LOAD
AD9753
REFERENCE
SECTION
AVDD
0.1F
1.2V REF
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
IREF 2k
Figure 4. Internal Reference Configuration
AVDD
EXTERNAL
REFERENCE
IREF
AD9753
REFERENCE
SECTION
AVDD
1.2V REF
REFIO
FSADJ
CURRENT
SOURCE
ARRAY
2k
Figure 5. External Reference Configuration
REV. 0
–9–

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