AD9640-105EBZ Просмотр технического описания (PDF) - Analog Devices

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AD9640-105EBZ

14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

Analog Devices 

AD9640

ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,

DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.

Table 2.

Parameter

RESOLUTION

ACCURACY

No Missing Codes

Offset Error

Gain Error

Differential Nonlinearity (DNL)1

Integral Nonlinearity (INL)1

MATCHING CHARACTERISTIC

Offset Error

Gain Error

TEMPERATURE DRIFT

Offset Error

Gain Error

INTERNAL VOLTAGE REFERENCE

Output Voltage Error (1 V Mode)

Load Regulation @ 1.0 mA

INPUT REFERRED NOISE

VREF = 1.0 V

ANALOG INPUT

Input Span, VREF = 1.0 V

Input Capacitance2

VREF INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

AVDD, DVDD

DRVDD (CMOS Mode)

DRVDD (LVDS Mode)

Supply Current

I 1, 3

AVDD

I 1, 3

DVDD

I1

DRVDD

(3.3

V

CMOS)

I1

DRVDD

(1.8

V

CMOS)

I1

DRVDD

(1.8

V

LVDS)

POWER CONSUMPTION

DC Input

Sine Wave Input1 (DRVDD = 1.8 V)

Sine Wave Input1 (DRVDD = 3.3 V)

Standby Power4

Power-Down Power

Temperature

Full

Full

Full

Full

Full

25°C

Full

25°C

25°C

25°C

Full

Full

Full

Full

25°C

Full

Full

Full

AD9640ABCPZ-125/

AD9640BCPZ-125

Min Typ

Max

14

Guaranteed

±0.3 ±0.6

±0.2 ±3.0

±0.9

±0.4

±5.0

±2

±0.4 ±0.7

±0.1 ±0.6

±15

±95

±2

±15

7

1.3

2

8

6

AD9640ABCPZ-150/

AD9640BCPZ-150

Min Typ

Max

14

Guaranteed

±0.3

±0.6

±0.2

±3.0

−0.95/+1.5

−0.4/+0.6

±5.0

±2

±0.4

±0.7

±0.2

±0.6

±15

±95

±3

±15

7

1.3

2

8

6

Unit

Bits

% FSR

% FSR

LSB

LSB

LSB

LSB

% FSR

% FSR

ppm/°C

ppm/°C

mV

mV

LSB rms

V p-p

pF

kΩ

Full

1.7

1.8

1.9

1.7 1.8

1.9

V

Full

1.7

3.3

3.6

1.7 3.3

3.6

V

Full

1.7

1.8

1.9

1.7 1.8

1.9

V

Full

385

419

mA

470

517

Full

42

50

mA

Full

44

53

mA

Full

22

27

mA

56

57

Full

750

846

820

938

mW

Full

810

895

mW

Full

910

1000

mW

Full

77

77

mW

Full

2.5

6

2.5

6

mW

1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.

3 The maximum limit applies to the combination of IAVDD and IDVDD currents.

4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND).

Rev. B | Page 6 of 52

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