RTL8139C Просмотр технического описания (PDF) - Realtek Semiconductor

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RTL8139C

REALTEK 3.3V SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENT

Realtek Semiconductor 

RTL8139C(L)

6.5 Interrupt Mask Register

(Offset 003Ch-003Dh, R/W)

This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt.

During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt.

ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit.

Bit

R/W

Symbol

Description

15

R/W

SERR

System Error Interrupt: 1 => Enable, 0 => Disable.

14

R/W

TimeOut

Time Out Interrupt: 1 => Enable, 0 => Disable.

13

R/W

LenChg

Cable Length Change Interrupt: 1 => Enable, 0 => Disable.

12-7

-

-

Reserved

6

R/W

FOVW

Rx FIFO Overflow Interrupt: 1 => Enable, 0 => Disable.

5

R/W

PUN/LinkChg Packet Underrun/Link Change Interrupt: 1 => Enable, 0 =>

Disable.

4

R/W

RXOVW

Rx Buffer Overflow Interrupt: 1 => Enable, 0 => Disable.

3

R/W

TER

Transmit Error Interrupt: 1 => Enable, 0 => Disable.

2

R/W

TOK

Transmit OK Interrupt: 1 => Enable, 0 => Disable.

1

R/W

RER

Receive Error Interrupt: 1 => Enable, 0 => Disable.

0

R/W

ROK

Receive OK Interrupt: 1 => Enable, 0 => Disable.

6.6 Interrupt Status Register

(Offset 003Eh-003Fh, R/W)

This register indicates the source of an interrupt when the INTA pin goes active. Enabling the corresponding bits in the Interrupt

Mask Register (IMR) allows bits in this register to produce an interrupt. When an interrupt is active, one of more bits in this

register are set to a “1”. The interrupt Status Register reflects all current pending interrupts, regardless of the state of the

corresponding mask bit in the IMR. Reading the ISR clears all interrupts. Writing to the ISR has no effect.

Bit

15

14

13

12 - 7

6

5

4

3

2

1

0

R/W

R/W

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Symbol

SERR

TimeOut

LenChg

-

FOVW

PUN/LinkChg

RXOVW

TER

TOK

RER

ROK

Description

System Error: Set to 1 when the RTL8139C(L) signals a system error

on the PCI bus.

Time Out: Set to 1 when the TCTR register reaches to the value of the

TimerInt register.

Cable Length Change: Cable length is changed after Receiver is

enabled.

Reserved

Rx FIFO Overflow: Set when an overflow occurs on the Rx status FIFO.

Packet Underrun/Link Change: Set to 1 when CAPR is written but

Rx buffer is empty, or when link status is changed.

Rx Buffer Overflow: Set when receive (Rx) buffer ring storage

resources have been exhausted.

Transmit (Tx) Error: Indicates that a packet transmission was

aborted, due to excessive collisions, according to the TXRR's setting

Transmit (Tx) OK: Indicates that a packet transmission is completed

successfully.

Receive (Rx) Error: Indicates that a packet has either CRC error or

frame alignment error (FAE). The collided frame will not be recognized

as CRC error if the length of this frame is shorter than 16 byte.

Receive (Rx) OK: In normal mode, indicates the successful completion

of a packet reception. In early mode, indicates that the Rx byte count of

the arriving packet exceeds the early Rx threshold.

2002/01/10

15

Rev.1.4

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