AD9548BCPZ-REEL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD9548BCPZ-REEL7 Datasheet PDF : 112 Pages
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AD9548
Parameter
Min
Typ
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
900
Phase-Frequency Detector (PFD) Rate
Frequency Multiplication Range
6
VCO Gain
70
High Frequency Path
Input Frequency Range
100.1
Minimum Input Slew Rate
200
Frequency Divider Range
1
Common-Mode Voltage
1
Differential Input Voltage Sensitivity
100
Input Capacitance
Input Resistance
Low Frequency Path
Input Frequency Range
Minimum Input Slew Rate
3
2.5
3.5
50
Common-Mode Voltage
1.2
Differential Input Voltage Sensitivity
100
Input Capacitance
3
Input Resistance
4
Crystal Resonator Path
Crystal Resonator Frequency Range
10
Maximum Crystal Motional Resistance
Max
1000
150
255
500
8
100
50
100
Unit
MHz
MHz
MHz/V
MHz
V/μs
V
mV p-p
pF
kΩ
MHz
V/μs
V
mV p-p
pF
kΩ
MHz
Ω
Test Conditions/Comments
Assumes valid system clock and PFD rates
Minimum limit imposed for jitter
performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Minimum limit imposed for jitter
performance
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Fundamental mode, AT cut
See the System Clock Inputs section for
recommendations
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DISTRIBUTION CLOCK INPUTS (CLKINP/CLKINN)
Input Frequency Range
62.5
500
MHz
Minimum Slew Rate
75
V/μs
Minimum limit imposed for jitter
performance.
Common-Mode Voltage
700
mV
Internally generated.
Differential Input Voltage Sensitivity
100
mV p-p
Capacitive coupling required; can
accommodate single-ended input
by ac grounding unused input; the
instantaneous voltage on either pin
must not exceed the supply rails.
Differential Input Power Sensitivity
−15
dBm
The same as voltage sensitivity but
specified as power into a 50 Ω load.
Input Capacitance
3
pF
Input Resistance
5
kΩ
Each pin has a 2.5 kΩ internal dc-
bias resistance.
Rev. 0 | Page 6 of 112
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