AD9548BCPZ-REEL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD9548BCPZ-REEL7 Datasheet PDF : 112 Pages
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AD9548
Parameter
Incremental Power Dissipation
SYSCLK PLL Off
Input Reference On
Differential
Single-Ended
Output Distribution Driver On
LVDS
LVPECL
CMOS
Min Typ Max Unit Test Conditions/Comments
Conditions = typical configuration; table values show the
change in power due to the indicated operation.
−105
mW fSYSCLK = 1 GHz1; high frequency direct input mode.
7
mW
13
mW
70
mW
75
mW
65
mW A single 3.3 V CMOS output with a 10 pF load.
1 fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.
2 fS is the sample rate of the output DAC.
3 fDDS is the output frequency of the DDS.
LOGIC INPUTS (M7 TO M0, RESET, TDI, TCLK, TMS)
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS (M7 to M0, RESET, TDI, TCLK, TMS)
Input High Voltage (VIH)
2.1
V
Input Low Voltage (VIL)
0.8
V
Input Current (IINH, IINL)
±80
±200
μA
Input Capacitance (CIN)
3
pF
LOGIC OUTPUTS (M7 TO M0, IRQ, TDO)
Table 5.
Parameter
LOGIC OUTPUTS (M7 to M0, IRQ, TDO)
Output High Voltage (VOH)
Output Low Voltage (VOL)
IRQ Leakage Current
Active Low Output Mode
Active High Output Mode
Min
Typ
2.7
SYSTEM CLOCK INPUTS (SYSCLKP/SYSCLKN)
Max
Unit
Test Conditions/Comments
V
IOH = 1 mA
0.4
V
IOL = 1 mA
Open-drain mode
1
μA
VOH = 3.3 V
1
μA
VOL =-0 V
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
Min
Typ
500
1000
40
1.2
100
2
2.5
Max
1000
60
Unit
MHz
V/μs
%
V
mV p-p
pF
kΩ
Test Conditions/Comments
Minimum limit imposed for jitter
performance
Internally generated
Minimum voltage across pins required to
ensure switching between logic states;
the instantaneous voltage on either pin
must not exceed the supply rails; can
accommodate single-ended input by ac
grounding unused input
Single-ended, each pin
Rev. 0 | Page 5 of 112
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