AD9548BCPZ-REEL7(Rev0) Просмотр технического описания (PDF) - Analog Devices
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AD9548BCPZ-REEL7 Datasheet PDF : 112 Pages
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AD9548
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
As an Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
As an Output
Output Logic 1 Voltage
Output Logic 0 Voltage
SDO
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHI
Pulse Width Low, tLO
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup (tS)
CS to SCLK Hold (tC)
CS Minimum Pulse Width High
Min
Typ
Max
2.0
0.8
30
110
2
2.0
0.8
1
1
2
2.0
0.8
1
1
2
2.7
0.4
2.7
0.4
40
8
12
3
0
14
10
0
6
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 18.
Parameter
SDA, SCL (AS INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSP
Min
Typ
0.7 × DVDD3
−10
0.015 × DVDD3
Unit
Test Conditions/Comments
Internal 30 kΩ pull-up resistor
V
V
μA
μA
pF
Internal 30 kΩ pull-down resistor
V
V
μA
μA
pF
V
V
μA
μA
pF
V
1 mA load current
V
1 mA load current
V
1 mA load current
V
1 mA load current
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Max
Unit
V
0.3 × DVDD3 V
+10
μA
50
ns
Test Conditions/Comments
No internal pull-up/down resistor.
For VIN = 10% to 90% DVDD3
Rev. 0 | Page 11 of 112
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