AD9540(Rev0) Просмотр технического описания (PDF) - Analog Devices
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Компоненты Описание
производитель
AD9540 Datasheet PDF : 32 Pages
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Parameter
Min
FIN = 1966.08 MHz, FOUT = 491.52 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
>3 MHz
FIN = 2488 MHz, FOUT = 622 MHz
@ 10 Hz
@ 100 Hz
@ 1 kHz
@ 10 kHz
@ 100 kHz
@ 1 MHz
≥3 MHz
PHASE FREQUENCY DETECTOR/CHARGE PUMP
REFIN Input
Input Frequency2
÷M Set to Divide by at Least 4
÷M Bypassed
Input Voltage Levels
200
Input Capacitance
Input Resistance
CLK2 Input
Input Frequency
÷N Set to Divide by at Least 4
÷N Bypassed
Input Voltage Levels
200
Input Capacitance
Input Resistance
Charge Pump Source/Sink Maximum Current
Charge Pump Source/Sink Accuracy
Charge Pump Source/Sink Matching
Charge Pump Output Compliance Range3 0.5
STATUS Drive Strength
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
@ 2 MHz PFD Frequency
@ 100 MHz PFD Frequency
@ 200 MHz PFD Frequency
RF DIVIDER (CLK1 ) INPUT SECTION (÷R)
RF Divider Input Range
1
Input Capacitance (DC)
Input Impedance (DC)
Input Duty Cycle
42
Input Power/Sensitivity
−10
Input Voltage Level
200
Typ Max
105
112
122
130
141
144
146
100
108
115
125
135
140
142
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
AD9540
Test Conditions/Comments
RF Divider R = 4
RF Divider R = 4
655
200
450 600
10
1500
MHz
MHz
mV p-p
pF
Ω
450
1500
2
655
200
600
10
4
5
2
CPVDD − 0.5
MHz
MHz
mV p-p
pF
Ω
mA
%
%
V
mA
148
dBc/Hz
133
dBc/Hz
116
dBc/Hz
113
dBc/Hz
2700
3
1500
50
58
+4
1000
MHz
pF
Ω
%
dBm
mV p-p
DDS SYSCLK not to
exceed 400 MSPS
Single-ended, into a 50 Ω load4
Rev. 0 | Page 5 of 32
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