AD9540BCPZ-REEL7(RevC) Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

AD9540BCPZ-REEL7
(Rev.:RevC)

655 MHz Low Jitter Clock Generator

Analog Devices 

Data Sheet

Pin No.

21, 22, 23

28

29

31, 35

32

33

36

39

40

41

42

45

46

47

Paddle

Mnemonic

S0, S1, S2

CLK1

CLK1

CP_VDD

OUT0

OUT0

CP_OUT

REFIN

REFIN

CLK2

CLK2

CP_RSET

DRV_RSET

DAC_RSET

Exposed Paddle

AD9540

Description

Clock Frequency and Delay Select Pins. These pins specify one of eight clock frequency/delay

profiles.

RF Divider and Internal Clock Complementary Input.

RF Divider and Internal Clock Input.

Charge Pump and CML Driver Supply Pin. 3.3 V analog (clean) supply.

CML Driver Complementary Output.

CML Driver Output.

Charge Pump Output.

Phase Frequency Detector Reference Input.

Phase Frequency Detector Reference Complementary Input.

Phase Frequency Detector Oscillator (Feedback) Complementary Input.

Phase Frequency Detector Oscillator (Feedback) Input.

Charge Pump Current Set. Program charge pump current with a resistor to AGND.

CML Driver Output Current Set. Program CML output current with a resistor to AGND.

DAC Output Current Set. Program DAC output current with a resistor to AGND.

The exposed paddle on this package is an electrical connection as well as a thermal enhancement.

In order for the device to function properly, the paddle must be attached to analog ground.

Rev. C | Page 11 of 32

Share Link: