AD9540(Rev0) Просмотр технического описания (PDF) - Analog Devices
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производитель
AD9540 Datasheet PDF : 32 Pages
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AD9540
Parameter
51.84 MHz FOUT
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
> 1 MHz Offset
105 MHz Analog Out
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
155.52 MHz Analog Out
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ Max
Unit
Test Conditions/Comments
110
dBc/Hz
121
dBc/Hz
135
dBc/Hz
142
dBc/Hz
148
dBc/Hz
153
dBc/Hz
105
dBc/Hz
115
dBc/Hz
126
dBc/Hz
132
dBc/Hz
140
dBc/Hz
145
dBc/Hz
100
dBc/Hz
112
dBc/Hz
123
dBc/Hz
131
dBc/Hz
138
dBc/Hz
144
dBc/Hz
1 The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,
not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated.
2 Driving the PLLREF input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.
3 The charge pump output compliance range is functionally 0.2 V to (CPVDD − 0.2 V). The value listed here is the compliance range for 5% matching.
4 The input impedance of the CLK1 input is 1500 Ω. However, to provide matching on the clock line, an external 50 Ω load is used.
5 Measured as peak-to-peak between DAC outputs.
6 For a 4.02 kΩ resistor from DRV_RSET to GND.
7 IBIS models for the digital I/O pins available upon request.
8 Assumes a 1 mA load.
Rev. 0 | Page 8 of 32
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