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AD9540(Rev0) Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9540
(Rev.:Rev0)

655 MHz Low Jitter Clock Generator

Analog Devices

AD9540 Datasheet PDF : 32 Pages

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AD9540

SPECIFICATIONS

AVDD = DVDD = 1.8 V ± 5%; DVDD_I/O = CP_VDD = 3.3 V ± 5% (@ TA = 25°C), DAC_RSET = 3.92 kΩ, CP_RSET = 3.09 kΩ,

DRV_RSET = 4.02 kΩ, unless otherwise noted.

Table 1.

Parameter

Min

TOTAL SYSTEM JITTER AND PHASE NOISE FOR

105 MHz ADC CLOCK GENERATION CIRCUIT

Converter Limiting Jitter1

Resultant SNR

Phase Noise of Fundamental

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

≥1 MHz Offset

TOTAL SYSTEM PHASE NOISE FOR 210 MHz

ADC CLOCK GENERATION CIRCUIT

Phase Noise of Fundamental

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

TOTAL SYSTEM TIME JITTER FOR CLOCKS

155.52 MHz Clock

622.08 MHz Clock

RF DIVIDER/CML DRIVER EQUIVALENT

INTRINSIC TIME JITTER

FIN = 414.72 MHz, FOUT = 51.84 MHz

FIN = 1244.16 MHz, FOUT = 155.52 MHz

FIN = 2488.32 MHz, FOUT = 622.08 MHz

RF DIVIDER/CML DRIVER RESIDUAL PHASE NOISE

FIN = 81.92 MHz, FOUT = 10.24 MHz

@ 10 Hz

@ 100 Hz

@ 1 kHz

@ 10 kHz

@ 100 kHz

≥1 MHz

FIN = 983.04 MHz, FOUT = 122.88 MHz

@ 10 Hz

@ 100 Hz

@ 1 KHz

@ 10 kHz

@ 100 kHz

@ 1 MHz

>3 MHz

Typ Max

720

59.07

101

110

147

153

79.2

105

144

151

581

188

136

101

108

120

128

137

145

150

153

115

125

132

142

146

151

153

Unit

fS rms

dBc/Hz

Test Conditions/Comments

dBc/Hz

fS rms

dBc/Hz

12 kHz to 1.3 MHz bandwidth

12 kHz to 5 MHz bandwidth

R = 8, BW = 12 kHz to 400 kHz

R = 8, BW = 12 kHz to 1.3 MHz

R = 4, BW = 12 kHz to 5 MHz

RF Divider R = 8

Rev. 0 | Page 4 of 32

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