AD9524BCPZ Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9524BCPZ

Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

Analog Devices 

Data Sheet

AD9524

Parameter

Input Capacitance

Duty Cycle

Pulse Width Low

Pulse Width High

Min Typ Max Unit

1

pF

1.6

ns

1.6

ns

OSC_CTRL OUTPUT CHARACTERISTICS

Table 5.

Parameter

OUTPUT VOLTAGE

High

Low

Min

Typ

VDD3_PLL1 − 0.15

Test Conditions/Comments

Duty cycle bounds are set by pulse width high and pulse width low

Max

Unit Test Conditions/Comments

V

RLOAD > 20 kΩ

150

mV

REF_TEST INPUT CHARACTERISTICS

Table 6.

Parameter

Min

Typ

REF_TEST INPUT

Input Frequency Range

Input High Voltage

2.0

Input Low Voltage

Max

Unit Test Conditions/Comments

250

MHz

V

0.8

V

PLL1 CHARACTERISTICS

Table 7

Parameter

PLL1 FIGURE OF MERIT (FOM)

MAXIMUM PFD FREQUENCY

Antibacklash Pulse Width

Minimum and Low

Maximum and High

Min Typ

Max

Unit

−226

dBc/Hz

Test Conditions/Comments

75

MHz

75

MHz

PLL1 OUTPUT CHARACTERISTICS

Table 8.

Parameter1

Min

Typ

MAXIMUM OUTPUT FREQUENCY

250

Rise/Fall Time (20% to 80%)

387

Duty Cycle

45

50

OUTPUT VOLTAGE HIGH

VDD3_PLL1 − 0.25

VDD3_PLL1 − 0.1

OUTPUT VOLTAGE LOW

1 CMOS driver strength = strong (see Table 52).

Max

Unit Test Conditions/Comments

MHz

665

ps 15 pF load

55

% f = 250 MHz

Output driver static

V

Load current = 10 mA

V

Load current = 1 mA

Output driver static

0.2

V

Load current = 10 mA

0.1

V

Load current = 1 mA

Rev. D | Page 7 of 56

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