AD9524BCPZ Просмотр технического описания (PDF) - Analog Devices

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производитель

AD9524BCPZ

Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

Analog Devices 

Data Sheet

AD9524

Parameter

CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON

LVDS Mode, 7 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

LVDS Mode, 3.5 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

LVPECL Compatible Mode

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

HSTL Mode, 16 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

HSTL Mode, 8 mA

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

VDD3_OUT[x:y],1 Supply Voltage Clock Output Drivers

Min Typ Max

10 10.8

27 29.8

6.5 7.5

23 26.3

11 12.4

28 31.2

20 24.3

50 59.1

11 12.7

27 31.8

Unit Test Conditions/Comments

Channel x control register, Bit 4 = 1

mA f = 122.88 MHz

mA f = 983.04 MHz

mA f = 122.88 MHz

mA f = 983.04 MHz

mA f = 122.88 MHz

mA f = 983.04 MHz

mA f = 122.88 MHz

mA f = 983.04 MHz

mA f = 122.88 MHz

mA f = 983.04 MHz

1 x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0, OUT0 (Pin 41 and Pin 40,

respectively) and Supply Voltage Clock Output OUT1, OUT1 (Pin 38 and Pin 37, respectively).

2 The current for Pin 34 (VDD1.8_OUT[0:3]) is 2× that of the other VDD1.8_OUT[x:y] pairs.

Rev. D | Page 5 of 56

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