AD9524BCPZ Просмотр технического описания (PDF) - Analog Devices
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AD9524BCPZ Datasheet PDF : 56 Pages
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AD9524
Data Sheet
LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL
Table 13.
Parameter
Min
VOLTAGE
Input High
2.0
Input Low
INPUT LOW CURRENT
CAPACITANCE
RESET TIMING
Pulse Width Low
50
Inactive to Start of Register Programming 100
SYNC TIMING
Pulse Width Low
1.5
Typ Max
0.8
±80 ±250
3
Unit Test Conditions/Comments
V
V
µA
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing
out of the AD9524
pF
ns
ns
ns
High speed clock is CLK input signal
STATUS OUTPUT PINS—STATUS1, STATUS0
Table 14.
Parameter
Min
VOLTAGE
Output High
2.94
Output Low
Typ Max
0.4
Unit Test Conditions/Comments
V
V
SERIAL CONTROL PORT—SPI MODE
Table 15.
Parameter
Min
CS (INPUT)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SCLK (INPUT) IN SPI MODE
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)
Voltage
Input Logic 1
Input Logic 0
Current
Input Logic 1
Input Logic 0
Input Capacitance
Typ Max
2.0
0.8
30
−110
2
2.0
0.8
240
1
2
Unit Test Conditions/Comments
CS has an internal 40 kΩ pull-up resistor
V
V
µA
µA
The minus sign indicates that, due to the
internal pull-up resistor, current is flowing out
of the AD9524
pF
SCLK has an internal 40 kΩ pull-down resistor
in SPI mode but not in I2C mode
V
V
µA
µA
pF
2.0
V
0.8
V
1
µA
1
µA
2
pF
Rev. D | Page 10 of 56
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